Timing Issues

Digital Integrated
Circuits
Jan M. Rabaey
AAnantha
Design Perspective
Chandrakasan
Borivoje Nikoli
Timing Issues
January 2003
1
Digital
EE141 Integrated Circuits 2nd Timing Issues
Synchronous Timing
CLK
In Combinational
R1 R2
Cin Logic Cout Out
2
Digital
Timing
Definitions
3
Digital
Latch Parameters
D Q
Clk
T
Clk PW
tsu
D
thold
tc-q td-q
Q
Delays can be different for rising and falling data transitions

4
Digital
Register Parameters
D Q
Clk
T
Clk
D thold
tsu
tc-q
Q
Delays can be different for rising and falling data transitions

5
Digital
Clock Uncertainties
4 Power Supply
3 Interconnect
2 6 Capacitive Load
Devices
7 Coupling to Adjacent Lines

5 Temperature
1 Clock Generation
Sources of clock uncertainty
6
Digital
Clock Nonidealities
Clock skew
Spatial variation in temporally equivalent clock
edges; deterministic + random, tSK
Clock jitter
Temporal variations in consecutive edges of the
clock signal; modulation + random noise
Cycle-to-cycle (short-term) tJS
Long term tJL
Variation of the pulse width
Important for level sensitive clocking
7
Digital
Clock Skew and Jitter
Clk
tSK
Clk tJS
Both skew and jitter affect the effective cycle time

Only skew affects the race margin
8
Digital
Clock Skew
# of registers
Earliest occurrence
Latest occurrence
of Clk edge of Clk edge
Nominal /2 Nominal + /2
Insertion delay Clk delay

Max Clk skew
9
Digital
Positive and Negative Skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q
Logic Logic
CLK tCLK1 tCLK2 tCLK3
delay delay
(a) Positive skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q
Logic Logic
tCLK1 tCLK2 tCLK3
delay
(b) Negative skew
10
Digital
Positive Skew
TCLK
TCLK
1
CLK1
CLK2 2 4
th
Launching edge arrives before the receiving edge
11
Digital
Negative Skew
TCLK +
TCLK
1 3
CLK1
CLK2 2 4
Receiving edge arrives before the launching edge
12
Digital
Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic
CLK tCLK1 tCLK2
tc q tlogic
tc q, cd t
tsu, thold
Minimum cycle time:

T + > tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )
13
Digital
Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic
CLK tCLK1 tCLK2
tc q tlogic
tc q, cd t
tsu, thold
Hold time constraint:

thold + < t(c-q, cd) + t(logic, cd)
Worst case is when receiving edge arrives late
Race between data and clock
14
Digital
Impact of Jitter
TC LK

t j itter
CLK
-tji tte r
REGS Combinational
In Logic
CLK t log ic
tc-q , tc-q, cd t log ic, cd
ts u, thold
tjitter
15
Digital
Longest Logic Path in
Edge-Triggered Systems
TJI +
TSU
Clk
TClk-Q
Tlogic
T
Latest point Earliest arrival

of launching of next cycle
16
Digital
Clock Constraints in
Edge-Triggered Systems
If launching edge is late and receiving edge is early, the data will not be too late if:
T + 2TJI > Tc-q + Tlogic + TSU
Minimum cycle time is determined by the maximum delays through the logic
T > Tc-q + Tlogic + TSU - +

2 Skew
TJI can be either positive or negativ
17
Digital
Shortest Path
Earliest point
of launching
Clk
TClk-Q Tlogic
Clk
TH
Data must not arrive

Nominal
before this time
clock edge
18
Digital
How to counter Clock Skew?
Negative Skew
REG
REG
REG
. log Out
REG
In
Positive Skew

Clock Distribution
Data and Clock Routing
19
Digital
Flip-Flop Based Timing
Skew Flip-flop
Logic delay delay

TSU
Flip TClk-Q
-flop

Logic
Representation after
M. Horowitz, VLSI Circuits 1996.
20
Digital
Flip-Flops and Dynamic Logic
Logic delay
TSU
TSU TClk-Q
TClk-Q

Logic delay
Precharge Evaluate Precharge
Evaluate
Flip-flops are used only with static logic
21
Digital
Latch timing
tD-Q When data arrives
to transparent latch
Latch is a soft barrier
D Q
Clk
tClk-Q When data arrives

to closed latch
Data has to be re-launched
22
Digital
Single-Phase Clock with Latches

Latch
Logic
Tskl Tskl Tskt Tskt
Clk
PW
P
23
Digital
Latch-Based Design
L1 latch is L2 latch is transparent
transparent when = 1

when = 0
L1 L2
Logic
Latch Latch
Logic
24
Digital
Slack-borrowing
L1 L2 L1
In CLB_A CLB_B
D Q D Q D Q
a t p d,A b c t p d,B d e
CLK1 CLK2 CLK1

TC LK
CLK1
CLK2
slack passed to next stage

t pd,A tD Q tpd,B t DQ
e valid
a valid b valid c valid d valid
25
Digital
Latch-Based Timing
Skew
Static logic

L2 latch
L1
Logic
L2
Latch Latch
L1 latch
Logic
Long
path
Can tolerate skew!

Short
path
26
Digital
Clock Distribution
H-tree
CLK
Clock is distributed in a tree-like fashion

27
Digital
More realistic H-tree
[Restle98]
28
Digital
The Grid System
G CL K
D r iv e r
D r iv e r
G C LK
D riv e r
GC LK
No rc-matching
Large power
D r iv e r
G CL K
29
Digital
Example: DEC Alpha 21164
Clock Frequency: 300 MHz - 9.3 Million Transistors
Total Clock Load: 3.75 nF
Power in Clock Distribution network : 20 W (out of 50)
Uses Two Level Clock Distribution:
Single 6-stage driver at center of chip

Secondary buffers drive left and right side
clock grid in Metal3 and Metal4
Total driver size: 58 cm!
30
Digital
21164 Clocking
tcycle= 3.3ns 2 phase single wire clock,
trise = 0.35ns tskew = 150ps distributed globally
Clock waveform
2 distributed driver channels
Reduced RC delay/skew
final drivers Improved thermal distribution
3.75nF clock load
58 cm final driver width
Local inverters for latching
Conditional clocks in caches to
reduce power
pre-driver More complex race checking
Device variation
Location of clock
driver on die 31
Digital
Clock Drivers
32
Digital
Clock Skew in Alpha Processor
33
Digital
EV6 (Alpha 21264) Clocking
600 MHz 0.35 micron CMOS
tcycle= 1.67ns
trise = 0.35ns tskew = 50ps

Global clock waveform
2 Phase, with multiple conditional
buffered clocks
2.8 nF clock load
40 cm final driver width
Local clocks can be gated off to
save power
Reduced load/skew
Reduced thermal issues
PLL
Multiple clocks complicate race
checking
34
Digital
21264 Clocking
35
Digital
EV6 Clock Results ps
ps
5 300
10 305
15 310
20 315
25 320
30 325
35 330
40 335
45 340
50 345
GCLK Skew GCLK Rise Times

(at Vdd/2 Crossings) (20% to 80% Extrapolated to 0% to 100%)
36
Digital
EV7 Clock Hierarchy
Active Skew Management and Multiple Clock Domains
+ widely dispersed
NCLK
(Mem Ctrl) drivers
+ DLLs compensate
DLL
static and low-
DLL
DLL
frequency variation
+ divides design and

verification effort
- DLL design and

PLL
L2L_CLK
L2R_CLK
(L2 Cache)
(L2 Cache)
GCLK
(CPU Core)
verification is added
work
SYSCLK + tailored clocks
37
Digital
Self-timed and Asynchronous
Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
1) Completion is ensured by careful timing analysis

2) Ordering of events is implicit in logic
Self-timed design
1) Completion ensured by completion signal

2) Ordering imposed by handshaking protocol
38
Digital
Synchronous Pipelined Datapath
R1 R2 R3 R4
In Logic Logic
D Q Block #1 D Q Block #2 D Q D Q
CLK tpd,reg tpd1 tpd2 tpd3
39
Digital
Self-Timed Pipelined Datapath
Req Req Req Req
Ack HS Ack HS Ack HS ACK
Start Done Start Done Start Done
R1 F1 R2 F2 R3 F3 Out
In
tpF1 tpF2 tpF3
40
Digital
Completion Signal Generation
LOGIC
In Out
NETWORK
Start DELAY MODULE Done
Using Delay Element (e.g. in memories)
41
Digital
Completion Signal Generation
Using Redundant Signal Encoding
42
Digital
Completion Signal in DCVSL
VDD VDD
Start B0
Done
B1
B0 B1
In1
In1
In2 PDN PDN
In2
Start
43
Digital
Self-Timed Adder
VDD VDD
Start Start
P0 P1 P2 P3 Done
C0 C1 C2 C3 C4 C4
C4 C4
C0 G0 G1 G2 G3 C3 C3
Start C2 C2
C1 C1
VDD
Start
Start
P0 P1 P2 P3
C0 C1 C2 C3 C4 C4 (b) Completion signal
C0
K0 K1 K2 K3
Start
(a) Differential carry generation
44
Digital
Completion Signal Using Current Sensing
VDD
Input Register
Start
Inputs Static CMOS Logic Output tdelay
A
GNDsense toverlap
Start
Current Sensor A B
tMDG
Done tpd-NOR
Done
Min Delay Generator B
Output valid
45
Digital
Hand-Shaking Protocol
Req
Req
Ack
SENDER RECEIVER
Data 3
Ack
(a) Sender-receiver configuration Data 1 1
cycle 1 cycle 2
Senders action
Receivers action
(b) Timing diagram
Two Phase Handshake
46
Digital
Event Logic The Muller-C Element
A B Fn1
A
0 0 0
F 0 1 Fn
B 1 0 Fn
1 1 1
(a) Schematic (b) Truth table

VDD
VDD VDD
A B
A
S Q
F B
B F
R A F
B
(a) Logic
A B
B
(b) Majority Function
(c) Dynamic 47
Digital
2-Phase Handshake Protocol
Data
Sender Receiver
logic logic
Data ready Data accepted
Req
C
Ack
Handshake logic
Advantage : FAST - minimal # of signaling events (important for global

interconnect)
Disadvantage : edge - sensitive, has state
48
Digital
Example: Self-timed FIFO
In Out
R1 R2 R3
En Done
Reqi Req0
C C C
Acki Acko
All 1s or 0s -> pipeline empty

Alternating 1s and 0s -> pipeline full
49
Digital
2-Phase Protocol
50
Digital
Example
From [Horowitz]
51
Digital
Example
52
Digital
Example
53
Digital
Example
54
Digital
2 4 Senders action
Req
Receivers action
Ack
3 5
Data 1 1
Cycle 1 Cycle 2
Also known as RTZ

Slower, but unambiguous
55
Digital
Implementation using Muller-C elements
Data
Sender Receiver
logic logic
Data ready Data accepted
Req
S
C C
Ack
Handshake logic
56
Digital
Self-Resetting Logic
completion completion completion

detection detection detection
(L1) (L2) (L3)
Precharged Precharged Precharged
Logic Block Logic Block Logic Block
(L1) (L2) (L3)
VDD
Post-charge
int
out logic
A B C
57
Digital
Clock-Delayed Domino
GND
CLK1 CLK2 (to next stage)
VDD
Q1 (also D2)
D1 Pulldown
Network
58
Digital
Asynchronous-Synchronous Interface
fin
Synchronous system
Asynchronous
system
fCLK
Synchronization
59
Digital
Synchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events
occurred first
Synchronizer: Arbiter with clock as one of the
inputs
Problem: Circuit HAS to make a decision in
limited time - which decision is not important
Caveat: It is impossible to ensure correct
operation
But, we can decrease the error probability at the
expense of delay
60
Digital
A Simple Synchronizer
CLK
I1
int
D Q
I2
CLK
Data sampled on rising edge of the clock
Latch will eventually resolve the signal value,

but ... this might take infinite time!
61
Digital
Synchronizer: Output Trajectories
2.0
Vout
1.0
0.0
0 100 200 300
time [ps]
Single-pole model for a flip-flop
62
Digital
Mean Time to Failure
63
Digital
Example
Tf = 10 nsec = T
Tsignal = 50 nsec
tr = 1 nsec
t = 310 psec
VIH - VIL = 1 V (VDD = 5 V)
N(T) = 3.9 10-9 errors/sec

MTF (T) = 2.6 10 8 sec = 8.3 years
MTF (0) = 2.5 sec
64
Digital
Influence of Noise
Uniform distribution
around VM
p(v)
logarithmic
reduction
T
0 VIL VIH
Still Uniform
Initial Distribution
Low amplitude noise does not influence synchronization behavior
65
Digital
Typical Synchronizers
2 phase clocking circuit 2
Q
1
Q 2
Using delay line
66
Digital
Cascaded Synchronizers Reduce MTF
In O1 O2 Out
Sync Sync Sync
67
Digital
Arbiters
Req1 Ack1
Req1 A
Arbiter
Req2 Ack2 Ack2
B
Ack1
Req2
(a) Schematic symbol
Req1 (b) Implementation

Req2
VT gap
A (c) Timing diagram
B
metastable
Ack1
t
68
Digital
PLL-Based Synchronization
Chip 1 Chip 2
Data
Digital Digital
System System
reference
fsystem = N x fcrystal clock
Divider PLL
PLL Clock
Buffer
fcrystal 200<Mhz
Crystal
Oscillator
69
Digital
PLL Block Diagram
Reference Up
clock v
Phase Charge Loop
VCO
detector pump filter
Local Down
clock
Divide by
N
System
Clock
70
Digital
Phase Detector
Output before filtering
ref
ref
Output local
clock
local Output
clock
(a) (b)
Output (Low pass filtered)
VDD
Transfer
characteristic
-180 -90 90 180 phase error (deg)

(c)
71
Digital
Phase-Frequency Detector
B A
Rst UP
D Q B
A UP = 0 UP = 0 UP = 1
A
DN = 1 DN = 0 DN = 0
Rst
D Q
DN
A B
B
(a) schematic (b) state transition diagram
A A
B B
UP UP
DN DN
(c) Timing waveforms
72
Digital
PFD Response to Frequency
UP
DN
73
Digital
PFD Phase Transfer Characteristic
Average (UP-DN)
VDD
2 phase error (deg)
74
Digital
Charge Pump
VDD
UP To VCO Control Input
DN
75
Digital
PLL Simulation
ref
1.0
div
0.8
Control Voltage (V)
0.6 vco
0.4
ref
0.2
0.0 div
0 1 2 3 4 5
Time ( s)
vco
76
Digital
Clock Generation using DLLs
Delay-Locked Loop (Delay Line Based)
fREF U
Phase Charge
D DL
Det Pump
Filter
fO
Phase-Locked Loop (VCO-Based)

fREF U
PD D CP VCO
N Filter
fO
77
Digital
Delay Locked Loop
U
FREF Phase Charge C
PH D VCTRL VCDL
detect pump
FO
(a)
REF
OUT
UP
DN
PH
VCTRL
Delay
78
Digital
DLL-Based Clock Distribution
Digital
VCDL
Circuit
CP/LF
Phase
Detector
Digital
GLOBAL CLK VCDL
Circuit
CP/LF
Phase
Detector
79
Digital

Timing Issues

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Digital Integrated

Delays can be different for rising and falling data transitions

Delays can be different for rising and falling data transitions

7 Coupling to Adjacent Lines

Sources of clock uncertainty

Both skew and jitter affect the effective cycle time

Insertion delay Clk delay

CLK tCLK1 tCLK2 tCLK3

tCLK1 tCLK2 tCLK3

Launching edge arrives before the receiving edge

Receiving edge arrives before the launching edge

CLK tCLK1 tCLK2

Minimum cycle time:

CLK tCLK1 tCLK2

Hold time constraint:

Latest point Earliest arrival

T + 2TJI > Tc-q + Tlogic + TSU

T > Tc-q + Tlogic + TSU - +

Data must not arrive

Data and Clock Routing

Flip-flops are used only with static logic

tClk-Q When data arrives

Data has to be re-launched

Tskl Tskl Tskt Tskt

CLK1 CLK2 CLK1

slack passed to next stage

Can tolerate skew!

Clock is distributed in a tree-like fashion

Total Clock Load: 3.75 nF

Power in Clock Distribution network : 20 W (out of 50)

Uses Two Level Clock Distribution:

Single 6-stage driver at center of chip

trise = 0.35ns tskew = 50ps

GCLK Skew GCLK Rise Times

+ divides design and

- DLL design and

Truly asynchronous design

1) Completion is ensured by careful timing analysis

1) Completion ensured by completion signal

CLK tpd,reg tpd1 tpd2 tpd3

Ack HS Ack HS Ack HS ACK

Start Done Start Done Start Done

tpF1 tpF2 tpF3

Start DELAY MODULE Done

Using Delay Element (e.g. in memories)

Using Redundant Signal Encoding

(a) Differential carry generation

(a) Sender-receiver configuration Data 1 1

(a) Schematic (b) Truth table

(b) Majority Function

Data ready Data accepted

Advantage : FAST - minimal # of signaling events (important for global

All 1s or 0s -> pipeline empty

Also known as RTZ

Data ready Data accepted

completion completion completion

CLK1 CLK2 (to next stage)

Data sampled on rising edge of the clock

Latch will eventually resolve the signal value,

Single-pole model for a flip-flop

N(T) = 3.9 10-9 errors/sec

Using delay line

Req1 (b) Implementation

-180 -90 90 180 phase error (deg)