Design of FIR filter using ROBA(Rounding

Based Approximate) Multiplier

Department of Electronics & Communication Engineering

Gudlavalleru Engineering College

By Under the supervision of

Shabhana Begum Mr.M.Vijaya Kumar
M.Tech. (ES) Assistant professor
15481D5521 Department of E.C.E

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 Contents
Plan of action
Objective
Introduction
Block diagram of ROBA multiplier
Implementation of ROBA multiplier
Parallel Prefix Adder:Kogge stone adder
Block diagram of proposed system
RTL and Technology schematic
Simulation results of kogge stone adder, ROBA multiplier with KS adder,
FIR filter design
Work to be completed
Tools to be used
References
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 Plan of Action
S.No. Project Work to be carried out No. of
Weeks
1. Literature Survey 6
2. Implementation of ROBA multiplier 4
3. Design of FIR filter using ROBA Multiplier 4
4. Coding and verification results 8
5. Comparison of various multipliers 8
6. Writing paper for publication 4
7. Documentation 2
Total 36
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 Objective
The main objective of the project is to analyze the
performance of ROBA multiplier for DSP filtering.

To compare the performance of ROBA multiplier with other

approximate multipliers.

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Block Diagram of Proposed System

Figure 1: Block diagram of FIR filter

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 Introduction
The performance of a traditional arithmetic circuit has limits. In order to
further enhance performance , approximate arithmetic designs scarify accuracy
to reduce energy consumption and reduce the cost.
These approximate arithmetic designs can be used in error tolerance
applications or applications related to speech and image.
Multipliers are one of the primary sources of power consumption in DSP
applications such as FIR filters.

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Block diagram of ROBA Multiplier

Figure 2: Block diagram of ROBA multiplier

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 Implementation of ROBA Multiplier
The ROBA multiplier, which had high accuracy, was based on rounding of the
inputs to the form of 2n.
The multiplication of A by B may be rewritten as

In Fig.1 First, the signs of the inputs are determined, and for each negative
value, the absolute value is generated. Next, the rounding block extracts the
nearest value for each absolute value in the form of 2 n . Having determined the
rounding values, using three shifter blocks, the products Ar Br, Ar B, and
Br A were calculated.

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 The input bit width of the shifter blocks is n, while their outputs are 2n. A
single 2n-bit kogge stone adder is used to calculate the summation of Ar B
and Br A.
The output of this adder and the result of Ar Br are the inputs of the
subtractor block whose output is the absolute value of the output of the
proposed multiplier.
Finally, if the sign of the final multiplication result should be negative, the
output of the subtractor will be negated in the sign set block. To negate the
values, twos complement representation was used.

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 Parallel Prefix Adders(PPA)
Parallel prefix (or tree prefix) adders provide a good theoretical basis to make
a wide range of design trade-offs in terms of delay, area and power. Parallel
Prefix Adders (PPA) is designed by considering carry look adder as a base.

Figure 3:Parallel Prefix Adder mechanism

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 Example for PPA:Kogge Stone Adder
Kogge-Stone adder is a parallel prefix form carry look ahead adder. The
Kogge-Stone adder was developed by peter M. Kogge and Harold S. Stone.
Kogge-Stone adder has large area with minimum fan-out. The Kogge- Stone
adder is widely known as a parallel prefix adder that performs fast logical
addition.
Kogge-Stone adder is used for wide adders because of it shows the less delay
among other architectures.
The adders are built from generate and propagate (GP) blocks, black cells
(BC) blocks, eight gray cell (GC) blocks.

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1. GP block:

The generate and propagate block takes a pair of operand bits (a, b) as
inputs. Computes a pair of generate and propagate signals (g, p) as output.
Generate (Gi) indicates whether a carry is generated from that bit

Gi = Ai & Bi

Propagate (Pi) indicates whether a carry is propagated through that bit

Pi = Ai xor Bi

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2. BC block:
The black cell takes two pairs of generate and propagate signals (gi, pi) and (gj, pj)
as input. computes a pair of generate and propagate signals (g, p) as output
Gi.j = Gi + (Pi . Gj)
Pi.j = Pi . Pj

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3. GC block:
The gray cell takes two pairs of generate and propagate signals (Gi, Pi) and (Gj, Pj)
as inputs. Computes a generate signal G as output
Gi,j = Gi + (Pi . Gj)

Black Cell consists of both Generate and propagate where as Gray Cell consists
of Generate.

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 Architecture of Kogge Stone Adder
A 16-bit Kogge-Stone adder is built from 16 generate and propagate (GP) blocks,
37 black cells (BC) blocks, 16 (GC) blocks, 16 sum blocks. Kogge-Stone prefix
tree is one of the adders that use fewest logic levels.

Figure 4: Illustration of 16bit Kogge Stone Adder 15

Example for kogge stone Adder

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Figure 5: Example for kogge stone adder
 FIR filter design
In signal processing, there are many instances in which an input signal to a
system contains extra unnecessary content or additional noise which can
degrade the quality of the desired portion.
In such cases, we may remove or filter out the useless samples. Therefore,
common filtering objectives are to improve the quality of a signal, to extract
information from signals or to separate two or more signals previously
combined to make efficient use of an available communication channel.
In the FIR system, the impulse response is of finite duration, this means that it
has a finite number of nonzero terms .
The response of the FIR filter depends only on the present and past input
samples.

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FIR filter was designed and simulated using integer coefficients.
Corresponding equation for the FIR filter is

Figure 6: Block diagram of FIR filter

In the later implementations these integer coefficients will be replaced by the

actual filter coefficients of the designed filter. 18
RTL schematic of ROBA multiplier:

Figure 7:RTL schematic of ROBA multiplier

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Technology Schematic of ROBA multiplier:

Figure 8:Technology Schematic of ROBA multiplier

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RTL schematic of FIR filter using ROBA multiplier

Figure 9:RTL schematic of FIR filter using ROBA multiplier

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Technology Schematic of FIR filter using ROBA multiplier

Figure 10:Technology Schematic of FIR filter using ROBA multiplier

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Simulation result of Kogge stone Adder

Figure 11:Simulation result of Kogge stone Adder

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Simulation results for Gray and black cells

Figure 12:Simulation result of Gray cell

Figure 13:Simulation result of Black cell 24

Simulation result of ROBA multiplier

Figure 14: Simulation result for ROBA multiplier with Kogge stone Adder 25
Simulation result for FIR filter using ROBA multiplier

Figure 15:Simulation result for FIR filter using ROBA multiplier 26

 Table 1:Area and delay report of ROBA multiplier and FIR filter

Parameters ROBA with KS Adder FIR filter using ROBA Multiplier

Number of Slice LUTs 192 768

Number of IOs 130 226

Delay 10.168ns 11.228ns

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 Work to be Completed
FIR filter for speech signal application has to be implemented using ROBA
multiplier and power,speed and area analysis has to be done for the
implemented design.

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 Tools used
Software:

Xilinx ISE Simulator

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 References
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Pedram,"RoBA Multiplier: A Rounding-Based Approximate Multiplier for High
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Thank you

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