Outline

A Brief History
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams

1: Circuits & Layout CMOS VLSI Design Slide 1

A Brief History
1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2008
Intel Pentium 4 processor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society

1: Circuits & Layout CMOS VLSI Design Slide 2

Annual Sales
1018 transistors manufactured in 2003
100 million for every human on the planet
Global Semiconductor Billings

200
(Billions of US$)

150

100

50

0
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

1: Circuits & Layout CMOS VLSI Design Slide 3

Invention of the Transistor
During the first half of the twentieth century,
electronic circuits used large, expensive, power-
hungry, and unreliable vacuum tubes.
In 1947, John Bardeen and Walter Brattain built the
first functioning transistor at Bell Laboratories,
shown in Figure

1: Circuits & Layout CMOS VLSI Design Slide 4

 It was nearly classified as a military secret, but Bell
Labs publicly introduced the device the following
year.
We have called it the Transistor, T-R-A-N-S-I-S-T-O-R, because it
is a resistor or semiconductor device which can amplify electrical
signals as they are transferred through it from input to output
terminals. It is, if you will, the electrical equivalent of a vacuum tube
amplifier. But there the similarity ceases. It has no vacuum, no
filament, no glass tube. It is composed entirely of cold, solid
substances.

1: Circuits & Layout CMOS VLSI Design Slide 5

 Ten years later, Jack Kilby at Texas Instruments realized the
potential for miniaturization if multiple transistors could be built
on one piece of silicon.
His first prototype of an integrated circuit, constructed from a
germanium slice and gold wires.
The invention of the transistor earned the Nobel Prize in
Physics in 1956 for Bardeen, Brattain, and their supervisor
William Shockley.
Kilby received the Nobel Prize in Physics in 2000 for the
invention of the integrated circuit.
By the 1960s, Metal Oxide Semiconductor Field Effect
Transistors (MOSFETs) began to enter production.

1: Circuits & Layout CMOS VLSI Design Slide 6

 In 1963, Frank Wanlass at Fairchild described the
first logic gates using MOSFETs.
Fairchilds gates used both nMOS and pMOS
transistors, earning the name Complementary Metal
Oxide Semiconductor, or CMOS.
The circuits used transistors but consumed only
nano watts of power, six orders of magnitude less
than their bipolar counterparts.

1: Circuits & Layout CMOS VLSI Design Slide 7

 Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 18 months
1,000,000,000

100,000,000
Integration Levels
Pentium 4

SSI: 10 gates
Pentium III
10,000,000 Pentium II
Pentium Pro
Transistors

Pentium
Intel486
1,000,000

100,000
80286
Intel386
MSI: 1000 gates
8086
10,000

4004
8008
8080
LSI: 10,000 gates
1,000

VLSI: > 10k gates

1970 1975 1980 1985 1990 1995 2000

Year

1: Circuits & Layout CMOS VLSI Design Slide 8

Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration

1: Circuits & Layout CMOS VLSI Design Slide 9

Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

CMOS VLSI Design

Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

CMOS VLSI Design

 MOSFET
A Metal-Oxide-Semiconductor (MOS) structure is
created by superimposing several layers of
conducting and insulating materials to form a
sandwich-like structure.
These structures are manufactured using a series of
chemical processing steps involving:
Oxidation of the silicon
selective introduction of dopants
etching of metal wires and contacts.

CMOS VLSI Design Slide 12

Power Supply Voltage
GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

CMOS VLSI Design

Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

CMOS VLSI Design

Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

CMOS VLSI Design

Series and Parallel
nMOS: 1 = ON a a a a a
0 0 1 1
g1

pMOS: 0 = ON
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON
Series: both must be ON a a a a
a

Parallel: either can be ON g1

g2
0 0 1 1

0 1 0 1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

1: Circuits & Layout CMOS VLSI Design Slide 16

CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
CMOS VLSI Design
Complementary CMOS
Complementary CMOS logic gates
nMOS pull-down network
pMOS
pMOS pull-up network pull-up
network

a.k.a. static CMOS inputs

output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

1: Circuits & Layout CMOS VLSI Design Slide 18

Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS Y
A

Rule of Conduction Complements B

Pull-up network is complement of pull-down
Parallel -> series, series -> parallel

1: Circuits & Layout CMOS VLSI Design Slide 19

CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
CMOS VLSI Design
CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
CMOS VLSI Design
 Verilog Code for NOT Gate
// Not gate Switch Level Code
module notgate(y,x);
output y;
input x;
supply1 pwr;
supply0 gnd;
pmos(y,pwr,x);
nmos(y,gnd,x);
endmodule

1: Circuits & Layout CMOS VLSI Design Slide 22

 Verilog code
nmos n1(out, data, control); // instantiate a nmos switch
pmos p1(out, data, control); // instantiate a pmos switch
A CMOS switch is instantiated as shown in below,
cmos cl(out, data, ncontrol, pcontrol);//instantiate cmos gate
or
cmos (out, data, ncontrol, pcontrol); //no instance name given

supply1 vdd ;
supply0 gnd ;

1: Circuits & Layout CMOS VLSI Design Slide 23

 // Not Gate Stimulus
module test_notgate;
wire y;
reg x;
notgate test(y,x);
initial
begin
x=1'b0;
#10 x=1'b1;
end
endmodule

1: Circuits & Layout CMOS VLSI Design Slide 24

CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B

CMOS VLSI Design

CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

CMOS VLSI Design

CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

CMOS VLSI Design

CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

CMOS VLSI Design

CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

CMOS VLSI Design

 Nand gate Switch Level Code
module nandgate(out,x,y);
output out;
input x,y;
wire c;
supply1 pwr;
supply0 gnd;
pmos(out,pwr,x);
pmos(out,pwr,y);
nmos(c,gnd,x);
nmos(out,c,y);
endmodule

1: Circuits & Layout CMOS VLSI Design Slide 30

 Nand Gate Stimulus
module test_nandgate;
wire out;
reg x,y;
nandgate test(out,x,y);
initial
begin
x=1'b0;y=1'b0;
#10 x=1'b0;y=1'b1;
#10 x=1'b1;y=1'b0;
#10 x=1'b1;y=1'b1;
end
endmodule

1: Circuits & Layout CMOS VLSI Design Slide 31

CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

CMOS VLSI Design

 Nor gate Switch Level
Code
module norgate(out,x,y);
output out;
input x,y;
wire c;
supply1 pwr;
supply0 gnd;
pmos(c,pwr,x);
pmos(out,c,y);
nmos(out,gnd,x);
nmos(out,gnd,y);
endmodule

1: Circuits & Layout CMOS VLSI Design Slide 33

 Nor Gate Stimulus
module test_norgate;
wire out;
reg x,y;
norgate test(out,x,y);
initial
begin
x=1'b0;y=1'b0;
#10 x=1'b0;y=1'b1;
#10 x=1'b1;y=1'b0;
#10 x=1'b1;y=1'b1;
end
endmodule

1: Circuits & Layout CMOS VLSI Design Slide 34

3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

CMOS VLSI Design

3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

Y
A
B
C

CMOS VLSI Design

CMOS Gate Design
Activity:
Sketch a 4-input CMOS NAND gate

1: Circuits & Layout CMOS VLSI Design Slide 37

CMOS Gate Design
Activity:
Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

1: Circuits & Layout CMOS VLSI Design Slide 38

Compound Gates
Compound gates can do any inverting function
Ex: Y AgB C gD (AND-AND-OR-INVERT, AOI22)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

1: Circuits & Layout CMOS VLSI Design Slide 39

Example: O3AI
Y A B C gD

1: Circuits & Layout CMOS VLSI Design Slide 40

Example: O3AI
Y A B C gD

A
B
C D
Y
D
A B C

1: Circuits & Layout CMOS VLSI Design Slide 41

Signal Strength
Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network

1: Circuits & Layout CMOS VLSI Design Slide 42

Pass Transistors
Transistors can be used as switches

s d

s d

1: Circuits & Layout CMOS VLSI Design Slide 43

Pass Transistors
Transistors can be used as switches

g g=0 Input g = 1 Output

s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1

1: Circuits & Layout CMOS VLSI Design Slide 44

Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well

1: Circuits & Layout CMOS VLSI Design Slide 45

Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

1: Circuits & Layout CMOS VLSI Design Slide 46