Pin Configuration of 8086

8086 is 40 pin IC
HMOS technology
Approximately 29,000 transistors
Available in 3 clock frequencies
5 MHz, 8 MHz, 10 MHz
Modes of operation
Minimum mode
Small systems
Single processor
Bus control signals generated by the processor

Maximum mode
Medium to large systems
Two or more processors
External bus controller is used to generate bus control
signals
Pin Diagram
Some pins have common
functions in both the modes

Pin numbers 24-31 have

different functions in minimum
and maximum mode

Pin 33 determines the mode

Connected to ground
Maximum mode
Connected to +5 V-
Minimum mode
Pins common to Min/Max mode
Pin Symbol In/Out Description
numbers
1 and 20 GND - Pins are grounded

40 VCC - Supply voltage

+5 V 10%

19 CLK I Clock input

33% duty cycle

Clock frequency depends on CPU

model

33 I +5 V Minimum mode
MN/ MX
Ground Maximum mode
Pin Symbol In/Out Description
numbers
17 NMI I Non-maskable interrupt
Positive-edge triggered
18 INTR I Maskable interrupt
Level triggered
Active high
21 RESET I Active high
Must be active for at least four
clock cycles
Terminates current activity
Clears-PSW, IP, DS, ES, SS, IQ
SET- CS to FFFF
22 READY I Active high
Acknowledgement from slow
devices
23 I Examined by WAIT instruction
TEST 1-idle state ; 0-continue
processing
Pin Symbol In/ Description
numbers Ou
t
32 RD O 0-Read operation

39, 2-16 AD15, AD14- I/O Multiplexed address bus (A15-A0)

AD0 and data bus (D15-D0)

35-38 A19/S6-A16/S3 O Multiplexed address (A19-A16) and

status lines (S6-S3)
S6-0
S5-current setting of IF
S 4 S3 Segment Register
0 0 ES
0 1 SS
1 0 CS or none
1 1 DS
Pin Symbol In/ Description
numbers Ou

34 BHE / S7
t
O Multiplexed Bus High Enable
BHE
and Status line (S7)
S7-1
 Operation BHE A0 Data pins used
Write/ read a word
0 0 D15 - D 0 (One bus cycle)
at an even address
Write/ read a byte
1 0 D 7 - D 0 (One bus cycle)
at an even address
Write/ read a byte
0 1 D15 - D8 (One bus cycle)
at an odd address
Write/ read a word D15 - D8 (First bus cycle :
0 1
at an odd address Least significant byte on D15 - D8)
D 7 - D 0 (Next bus cycle :
1 0
Most significant byte on D 7 - D 0)
Pins for Minimum Mode
Pin Symbol In/Out Description
numbers

24 O Interrupt acknowledgement for

INTA INTR
Indicates recognition of interrupt
request

25 ALE O Outputs a pulse at the beginning of

the bus cycle
Indicates availability of valid
address
26 O Output during later part of the bus
DEN cycle
Informs the transceivers that CPU
is ready to send or receive the data
Pins for Minimum Mode
Pin Symbol In/Out Description
numbers

27 DT/ R O Indicates transceivers to transmit or

receive data
1-transmit
0-receive

28 M/ IO O Distinguishes memory transfer from

I/O transfer
1-memory
0-I/O
29 O 0-write operation
WR
Pins 28, 29, 32 indicate the type of transfer

M/ IO RD WR
0 0 1 I/ O Read
0 1 0 I/ O Write
1 0 1 Memory Read
1 1 0 Memory Write
Pins for Minimum Mode
Pin Symbol In/Out Description
numbers

31 HOLD I 1-another master is requesting the

bus access
NO control of the bus until this
signal goes low

30 HLDA O Hold acknowledgement signal

Following pins are put in high
impedance state

AD0-AD19
BHE / S7, RD, WR, M/ IO
DEN, DT/ R, INTA
Minimum Mode System
Application of 8282 latches
8282 : 20 pin IC, 8 bit latch
Latching accomplished using 3 Intel-8282

20-bit address ready to be latched

ALE (Address Latch Enable)
8282s STB is connected to 8086s ALE

Active low OE is grounded to enable the latches

IC 74LS373 another commonly used octal latch

Application of 8286 transceivers
When OE 1, transceiver is
disabled
When OE 0,
T=1, transmitter
T=0, receiver

8286s OE 0 connected with

8086s DEN
8286s T connected with 8086s
DT/ R

2- 8286 are connected

20 pin IC
Increase current sourcing/sinking
capacity
8284A clock generator
18-pin IC
External oscillator connected
across X1 and X2
EFI is connected to external
clock frequency input
CLK is one-third of the input
frequency
When F/ C 1, EFI
determines the frequency
When F/ C 0, oscillator
input determines the
frequency
Main functions
CLK generation
RESET synchronization
Bus Cycle
Bus cycle time required for single read/write operation between

microprocessor and external memory(or I/O)

T-state one cycle of the clock

Read cycle
Transfer data from Memory (I/O) to processor

Write cycle
Transfer data from processor to Memory (I/O)

Length of bus cycle - 4 clock cycles (T 1,T2,T3,T4)

If Bus inactive between two Bus cycles

Idle state clock cycles (T I)

When READY is zero, Tw inserted between T3 and T4

Read Cycle
Write Cycle
Pins for Maximum Mode
Pin Symbol In/Out Description
numbers

24,25 QS1,QS0 O Reflects the status of the instruction

queue

QS1 QS0
No instruction was taken
0 0
from the queue
First byte of current instruction
0 1
was taken from the queue
Queue was flushed because
1 0
of a transfer instruction
A byte other than the first byte
1 1
was taken from the queue
Pins for Maximum Mode
Pin Symbol In/Out Description
numbers

26,27,28 O Indicates the type of transfer

S0, S1, S2 during current bus cycle

S2 S1 S0
0 0 0 Interrupt acknowledge
0 0 1 Read I/ O port
0 1 0 Write I/ O port
0 1 1 Halt
1 0 0 Instruction fetch
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Inactive
Pins for Maximum Mode
Pin Symbol In/Out Description
numbers
29 O Indicates that bus is not to be
LOCK
relinquished to other potential
masters
Initiated by LOCK instruction prefix
Maintained until end of the next
instruction

30 I/O For inputting bus requests and

RQ GT1 outputting bus grants

31 I/O Same as RQ GT1, but has higher

RQ GT 0 priority
Maximum Mode System
Read cycle
Write cycle