ARM Processors and Architectures - Uni Program

ARM Processors and
Architectures
A Comprehensive Overview
ARM University Program
September 2012
University Program Material

Copyright ARM Ltd 2012 1
Agenda
Introduction
ARM Architecture Overview
ARMv7-AR Architecture
Programmers Model
Memory Systems
ARMv7-M Architecture
Programmers Model
Memory Systems
Floating Point Extensions
ARM System Design
Software Development Tools

ARM Ltd
ARM founded in November 1990
Advanced RISC Machines
Company headquarters in Cambridge, UK

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Best known for its range of RISC processor cores designs

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develop and ship ARM-based SoCs
ARM does not manufacture silicon
More information about ARM and our offices on our web site:
http://www.arm.com/aboutarm/

ARM Offices Worldwide

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Embedded Processors

Application Processors

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Development of the ARM Architecture
v4 v5 v6 v7
Halfword and Improved SIMD Instructions
Thumb-2
signed halfword interworking Multi-processing
/ byte support CLZ v6 Memory
Architecture Profiles
Saturated arithmetic architecture
System mode DSP MAC Unaligned data support 7-A - Applications
instructions 7-R - Real-time
Thumb Extensions: 7-M - Microcontroller
instruction set Extensions: Thumb-2 (6T2)
(v4T) Jazelle (5TEJ) TrustZone (6Z)
Multicore (6K)
Thumb only (6-M)
Note that implementations of the same architecture can be different

Cortex-A8 - architecture v7-A, with a 13-stage pipeline
Cortex-A9 - architecture v7-A, with an 8-stage pipeline

Architecture ARMv7 profiles
Application profile (ARMv7-A)
Memory management support (MMU)
Highest performance at low power
Influenced by multi-tasking OS system requirements
TrustZone and Jazelle-RCT for a safe, extensible system
e.g. Cortex-A5, Cortex-A9
Real-time profile (ARMv7-R)

Protected memory (MPU)
Low latency and predictability real-time needs
Evolutionary path for traditional embedded business
e.g. Cortex-R4
Microcontroller profile (ARMv7-M, ARMv7E-M, ARMv6-M)

Lowest gate count entry point
Deterministic and predictable behavior a key priority
Deeply embedded use
e.g. Cortex-M3

Which architecture is my processor?

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Architecture ARMv7-AR profiles
Application profile (ARMv7-A)
Memory management support (MMU)
Highest performance at low power
Influenced by multi-tasking OS system requirements
e.g. Cortex-A5, Cortex-A8, Cortex-A9, Cortex-A15
Real-time profile (ARMv7-R)

Protected memory (MPU)
Low latency and predictability real-time needs
Evolutionary path for traditional embedded business
e.g. Cortex-R4, Cortex-R5

Cortex-A8
ARMv7-A Architecture
Thumb-2
Thumb-2EE (Jazelle-RCT)
TrustZone extensions
Custom or synthesized design
MMU
64-bit or 128-bit AXI Interface
L1 caches
16 or 32KB each
Unified L2 cache
0-2MB in size
8-way set-associative
Optional features
VFPv3 Vector Floating-Point
NEON media processing engine
Dual-issue, super-scalar 13-stage pipeline
Branch Prediction & Return Stack
NEON and VFP implemented at end of pipeline

Cortex-A9
ARMv7-A Architecture
Thumb-2, Thumb-2EE
TrustZone support
Variable-length Multi-issue
pipeline
Register renaming
Speculative data prefetching
Branch Prediction & Return
Stack
64-bit AXI instruction and data
interfaces
Optional features:
TrustZone extensions
PTM instruction trace interface
L1 Data and Instruction caches IEM power saving support
16-64KB each Full Jazelle DBX support
4-way set-associative VFPv3-D16 Floating-Point Unit (FPU) or
NEON media processing engine

Cortex-A15 MPCore
1-4 processors per cluster
Fixed size L1 caches (32KB)
Integrated L2 Cache
512KB 4MB
System-wide coherency
support with AMBA 4 ACE
Backward-compatible with
AXI3 interconnect
Integrated Interrupt Controller
0-224 external interrupts for
entire cluster
CoreSight debug
Advanced Power Management
Large Physical Address Extensions (LPAE) to ARMv7-A Architecture
Virtualization Extensions to ARMv7-A Architecture

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Data Sizes and Instruction Sets
ARM is a 32-bit load / store RISC architecture
The only memory accesses allowed are loads and stores
Most internal registers are 32 bits wide
Most instructions execute in a single cycle
When used in relation to ARM cores
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
Doubleword means 64 bits (eight bytes)
ARM cores implement two basic instruction sets

ARM instruction set instructions are all 32 bits long
Thumb instruction set instructions are a mix of 16 and 32 bits
Thumb-2 technology added many extra 32- and 16-bit instructions to the original 16-bit Thumb instruction
set
Depending on the core, may also implement other instruction sets

VFP instruction set 32 bit (vector) floating point instructions
NEON instruction set 32 bit SIMD instructions
Jazelle-DBX - provides acceleration for Java VMs (with additional software support)
Jazelle-RCT - provides support for interpreted languages
Processor Modes
ARM has seven basic operating modes
Each mode has access to its own stack space and a different subset of registers
Some operations can only be carried out in a privileged mode
Mode Description
Supervisor Entered on reset and when a Supervisor call
(SVC) instruction (SVC) is executed
Exception modes
Entered when a high priority (fast) interrupt is

FIQ
raised
IRQ Entered when a normal priority interrupt is raised

Privileged
modes
Abort Used to handle memory access violations
Undef Used to handle undefined instructions
Privileged mode using the same registers as User

System
mode
Mode under which most Applications / OS tasks Unprivileged
User
run mode

The ARM Register Set
User mode IRQ FIQ Undef Abort SVC
r0
r1
r2 ARM has 37 registers, all 32-bits long
r3
r4 A subset of these registers is accessible in
r5 each mode
r6 Note: System mode uses the User mode
r7 register set.
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
Current mode Banked out registers

Program Status Registers
31 28 27 24 23 19 16 15 10 9 8 7 6 5 4 0
N Z C V Q [de] J GE[3:0] IT[abc] E A I F T mode

f s x c
Condition code flags T bit
N = Negative result from ALU T = 0: Processor in ARM state
Z = Zero result from ALU T = 1: Processor in Thumb state
C = ALU operation Carried out J bit
V = ALU operation oVerflowed J = 1: Processor in Jazelle state
Mode bits
Sticky Overflow flag - Q flag Specify the processor mode
Indicates if saturation has occurred Interrupt Disable bits
I = 1: Disables IRQ
SIMD Condition code bits GE[3:0] F = 1: Disables FIQ
Used by some SIMD instructions E bit
E = 0: Data load/store is little endian
IF THEN status bits IT[abcde] E = 1: Data load/store is bigendian
Controls conditional execution of A bit
Thumb instructions A = 1: Disable imprecise data aborts

Instruction Set basics
The ARM Architecture is a Load/Store architecture
No direct manipulation of memory contents
Memory must be loaded into the CPU to be modified, then written back out
Cores are either in ARM state or Thumb state

This determines which instruction set is being executed
An instruction must be executed to switch between states
The architecture allows programmers and compilation tools to reduce

branching through the use of conditional execution
Method differs between ARM and Thumb, but the principle is that most (ARM) or all
(Thumb) instructions can be executed conditionally.

Data Processing Instructions
These instructions operate on the contents of registers
They DO NOT affect memory
arithmetic logical move
ADC SBC BIC ORR MVN
manipulation
(has destination ADD SUB RSB AND EOR MOV
register) RSC
ORN
comparison CMN CMP TST TEQ

(set flags only) (ADDS) (SUBS) (ANDS) (EORS)
Syntax:
<Operation>{<cond>}{S} {Rd,} Rn, Operand2
Examples:
ADD r0, r1, r2; r0 = r1 + r2
TEQ
University r0,
Program r1
Material ; if r0 = r1, Z flag will be set
Single Access Data Transfer
Use to move data between one or two registers and memory
LDRDSTRD Doubleword
LDR STR Word
Memory
LDRBSTRB Byte
LDRHSTRH Halfword
LDRSB Signed byte load
31 0
LDRSH Signed halfword load
Upper bits zero filled or
Rd sign extended on Load
Syntax:
LDR{<size>}{<cond>} Rd, <address>
STR{<size>}{<cond>} Rd, <address>
Example:
LDRB r0, [r1] ; load bottom byte of r0 from the
; byte of memory at address in r1
Multiple Register Data Transfer
These instructions move data between multiple registers and memory
Syntax
<LDM|STM>{<addressing_mode>}{<cond>} Rb{!}, <register list>
4 addressing modes (IA) IB DA DB
Increment after/before
r4
Decrement after/before
r4 r1
r1 r0 Increasing
Base Register (Rb) r10 r0 r4 Address
r1 r4
r0 r1
r0
Also
PUSH/POP, equivalent to STMDB/LDMIA with SP! as base register
Example
LDM r10, {r0,r1,r4} ; load registers, using r10 base
PUSH {r4-r6,pc} ; store registers, using SP base

Subroutines
Implementing a conventional subroutine call requires two steps
Store the return address
Branch to the address of the required subroutine
These steps are carried out in one instruction, BL
The return address is stored in the link register (lr/r14)
Branch to an address (range dependent on instruction set and width)
Return is by branching to the address in lr
func1 func2
void func1 (void)
{
: :
BL func2 :
func2(); BX lr
:
:
}

Supervisor Call (SVC)
SVC{<cond>} <SVC number>
Causes an SVC exception
The SVC handler can examine the SVC number to decide what operation
has been requested
But the core ignores the SVC number
By using the SVC mechanism, an operating system can implement a set

of privileged operations (system calls) which applications running in user
mode can request
Thumb version is unconditional

Exception Handling
When an exception occurs, the core
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
Change to ARM state (if appropriate)
0x1C FIQ
Change to exception mode
Disable interrupts (if appropriate) 0x18 IRQ
Stores the return address in LR_<mode> 0x14 (Reserved)
Sets PC to vector address 0x10 Data Abort
0x0C Prefetch Abort
To return, exception handler needs to 0x08 Supervisor Call
Restore CPSR from SPSR_<mode> 0x04 Undefined Instruction
Restore PC from LR_<mode> 0x00 Reset
Vector Table
Cores can enter ARM state or Thumb state when
taking an exception Vector table can also be at
0xFFFF0000 on most cores
Controlled through settings in CP15
Note that v7-M and v6-M exception model is different

Exception handling process
1. Save processor status
Main Copies CPSR into SPSR_<mode>
Application Stores the return address in LR_<mode>
s

tu
Adjusts LR based on exception type
ta
us r s
at o
2. Change processor status for exception

st ss
e ce
ng ro
Mode field bits

ha p
C ave
ARM or Thumb state

Interrupt disable bits (if appropriate)
Exception Sets PC to vector address
handler
3. Execute exception handler
R
et
<users code>
ur
n
fr o 4. Return to main application
m
ex
ce
Restore CPSR from SPSR_<mode>
pt
io
n Restore PC from LR_<mode>
. 1 and 2 performed automatically by the core
. 3 and 4 responsibility of software

What is NEON?
NEON is a wide SIMD data processing architecture
Extension of the ARM instruction set (v7-A)
32 x 64-bit wide registers (can also be used as 16 x 128-bit wide registers)
NEON instructions perform Packed SIMD processing

Registers are considered as vectors of elements of the same data type
Data types available: signed/unsigned 8-bit, 16-bit, 32-bit, 64-bit, single prec. float
Instructions usually perform the same operation in all lanes
Source
Source
Registers
Registers
Dn
Elements
Dm
Operation
Dd
Destination
Register
Lane

NEON Coprocessor registers
NEON has a 256-byte register file
Separate from the core registers (r0-r15)
Extension to the VFPv2 register file (VFPv3)
Two different views of the NEON registers

32 x 64-bit registers (D0-D31)
16 x 128-bit registers (Q0-Q15) D0
Q0
D1
Enables register trade-offs D2

Q1
Vector length can be variable D3
Different registers available
: :
D30
Q15
D31

NEON vectorizing example
How does the compiler perform vectorization?
void add_int(int * __restrict pa, 2. Unroll the loop to the appropriate
int * __restrict pb,
unsigned int n, int
number of iterations, and perform other
x) transformations like pointerization
void add_int(int *pa, int *pb,
{
unsigned n, int x)
unsigned int i;
{
for(i = 0; i < (n & ~3); i++)
unsigned int i;
pa[i] =each
1. Analyze pb[i] + x;
loop: for (i = ((n & ~3) >> 2); i; i--)
}
Are pointer accesses safe for {
*(pa + 0) = *(pb + 0) + x;
vectorization? *(pa + 1) = *(pb + 1) + x;
What data types are being used? *(pa + 2) = *(pb + 2) + x;
How do they map onto NEON *(pa + 3) = *(pb + 3) + x;
pa += 4; pb += 4;
vector registers?
}
Number of loop iterations } pb
3. Map each unrolled operation onto + + + + +

a NEON vector lane, and generate
corresponding NEON instructions pa
127 0
Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Memory Types
Each defined memory region will specify a memory type
The memory type controls the following:

Memory access ordering rules
Caching and buffering behaviour
There are 3 mutually exclusive memory types:

Normal
Device
Strongly Ordered
Normal and Device memory allow additional attributes for specifying

The cache policy
Whether the region is Shared
Normal memory allows you to separately configure Inner and Outer cache policies
(discussed in the Caches and TCMs module)

L1 and L2 Caches
I-Cache RAM L2 Cache
MMU/MPU
Off-chip
ARM Core Memory
On-chip
BIU
SRAM
D-Cache RAM
L1 L2 L3
Typical memory system can have multiple levels of cache

Level 1 memory system typically consists of L1-caches, MMU/MPU and TCMs
Level 2 memory system (and beyond) depends on the system design
Memory attributes determine cache behavior at different levels
Controlled by the MMU/MPU (discussed later)
Inner Cacheable attributes define memory access behavior in the L1 memory
system
Outer Cacheable attributes define memory access behavior in the L2 memory
system (if external) and beyond (as signals on the bus)
Before caches can be used, software setup must be performed

ARM Cache Features
Harvard Implementation for L1 caches
Separate Instruction and Data caches
Cache Lockdown
Prevents line Eviction from a specified Cache Way (discussed later)
Pseudo-random and Round-robin replacement strategies

Unused lines can be allocated before considering replacement
Non-blocking data cache

Cache Lookup can hit before a Linefill is complete (also checks Linefill buffer)
Streaming, Critical-Word-First
Cache data is forwarded to the core as soon as the requested word is received in
the Linefill buffer
Any word in the cache line can be requested first using a WRAP burst on the bus
ECC or parity checking

Example 32KB ARM cache
Address
Tag Set (= Index) Word Byte
31 13 12 5 4 2 1 0
19 8 3
Cache line
7 6 5 4 3 2 1 0 d
Tag v Data d
Tag vv
Tag Data d
Data
Line 0 d Cache has 8 words of data in each line
Tag v DataLine 0 d
Counter
Line 1 Line 0
LineLine
1 0 Each cache line contains Dirty bit(s)
Victim
Line 1
Line 1
Line 254
Indicates whether a particular cache
Line 30
LineLine
25530 line was modified by the ARM core
LineLine
31 30
Line 31
Line 31 Each cache line can be Valid or invalid
An invalid line is not considered
when performing a Cache Lookup
v - valid bit d - dirty bit(s)

Cortex MPCore Processors
Standard Cortex cores, with additional logic to support MPCore
Available as 1-4 CPU variants
Include integrated
Interrupt controller
Snoop Control Unit (SCU)
Timers and Watchdogs

Snoop Control Unit
The Snoop Control Unit (SCU) maintains coherency between L1 data caches
Duplicated Tag RAMs keep track of what data is allocated in each CPUs cache
Separate interfaces into L1 data caches for coherency maintenance
Arbitrates accesses to L2 AXI master interface(s), for both instructions and data
Optionally, can use address filtering

Directing accesses to configured memory range to AXI Master port 1
AXI Master 0 AXI Master 1

Snoop Control Unit
TAG TAG TAG TAG
D$ I$ D$ I$ D$ I$ D$ I$
CPU0 CPU1 CPU2 CPU3

Interrupt Controller
MPCore processors include an
integrated Interrupt Controller (IC)
Implementation of the Generic External Interrupt Legacy IRQ and
Interrupt Controller (GIC) Sources FIQ Signals
architecture
.......
The IC provides:
Interrupt Controller
Configurable number of external
nIRQ nFIQ
interrupts (max 224)
Interrupt prioritization and pre-
emption Global Private
Interrupt routing to different cores Timer Timer
CPU {n}
Private
Watchdog
Enabled per CPU
When not enabled, that CPU will use
legacy nIRQ[n] and nFIQ[n] signals

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

ARMv7-M Profile Overview
v7-M Cores are designed to support the microcontroller market
Simpler to program entire application can be programmed in C
Fewer features needed than in application processors
Register and ISA changes from other ARM cores

No ARM instruction set support
Only one set of registers
xPSR has different bits than CPSR
Different modes and exception models

Only two modes: Thread mode and Handler mode
Vector table is addresses, not instructions
Exceptions automatically save state (r0-r3, r12, lr, xPSR, pc) on the stack
Different system control/memory layout

Cores have a fixed memory map
No coprocessor 15 controlled through memory mapped control registers
Cortex-M3
Thumb-2 only
Fully programmable in C
3-stage pipeline
von Neumann architecture
Optional MPU
AHB-Lite bus interface
Fixed memory map
1-240 interrupts
Configurable priority levels
Non-Maskable Interrupt support
Debug and Sleep control
Serial wire or JTAG debug
Optional ETM
Cortex M3 Total
60k* Gates
Cortex-M0
16-bit Thumb-2 with system control
instructions
Fully programmable in C
3-stage pipeline
von Neuman architecture
AHB-Lite bus interface
Fixed memory map
1-32 interrupts
Configurable priority levels
Non-Maskable Interrupt support
Low power support
Core configured with or without
debug
Variable number of watchpoints and
breakpoints
Cortex M3 Total
60k* Gates
Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Processor Register Set
R0 Registers R0-R12
R1
General-purpose registers
R2
R3
R4 R13 is the stack pointer (SP) - 2 banked versions
R5
R6
R14 is the link register (LR)
R7
R8
R9 R15 is the program counter (PC)
R10
R11 PSR (Program Status Register)
R12
R13 (SP)
Not explicitly accessible
R14 (LR) Saved to the stack on an exception
R15 (PC)
Subsets available as APSR, IPSR, and EPSR
PSR

Special Purpose Registers
Program Status Register
Described in upcoming slides
Special Purpose Mask Registers : PRIMASK, FAULTMASK, BASEPRI

Used to modify exception priorities
To set/clear PRIMASK and FAULTMASK, use CPS instructions
CPSIE i / CPSID i / CPSIE f / CPSID f
Special Purpose CONTROL Register

2 bits
Bit 0 defines Thread mode privilege
Bit 1 defines Thread mode stack
The Special Purpose Registers are not memory-mapped
Accessed via specific instructions

MRS Move special purpose register to general-purpose register
MSR Move general-purpose register to special purpose register
xPSR - Program Status Register
31 28 27 26 25 24 23 20 19 16 15 10 9 8 0
N Z C V Q IT T GE[3:0] IT/ICI ISR Number
xPSR stored on stack during exceptions

Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation carry out
V = ALU operation overflow
Q = Saturated math overflow
IT/ICI bits
Contain IF-THEN base condition code or Interrupt Continue information
ISR Number
Stacked xPSR shows which exception was pre-empted
T=1

System Timer SysTick
Flexible system timer
24-bit self-reloading down counter
Reload on count == 0
Optionally cause SysTick interrupt on count == 0
Reload register
Calibration value
Clock source is CPU clock or optional external timing reference

Software selectable if provided
Reference pulse widths High/Low must exceed processor clock period
Counted by sampling on processor clock
Calibration Register provides value required for 10ms interval

STCALIB inputs tied to appropriate value

Modes Overview
ARM Processor
Application Code
Thread Reset
Mode
Exception Exception
Entry Return
Exception Code
Handler
Mode
Not shown: Handler mode can also be re-entered on exception return

Instruction Set Examples:
Data Processing:
MOV r2, r5 ; r2 = r5
ADD r5, #0x24 ; r5 = r5 + 36
ADD r2, r3, r4, LSL #2 ; r2 = r3 + (r4 * 4)
LSL r2, #3 ; r2 = r2 * 8
MOVT r9, #0x1234 ; upper halfword of r9 = #0x1234
MLA r0, r1, r2, r3 ; r0 = (r1 * r2) + r3
Memory Access:
STRB r2, [r10, r1] ; store lower byte in r2 at
address {r10 + r1}
LDR r0, [r1, r2, LSL #2] ; load r0 with data at address
{r1 + r2 * 4}
Program Flow:
BL<label> ; PC relative branch to <label>
location, and return address stored
in LR (r14)

Exception Handling
Exception types:
Reset
Non-maskable Interrupts (NMI)
Faults
PendSV
SVCall
External Interrupt
SysTick Interrupt
Exceptions processed in Handler mode (except Reset)

Exceptions always run privileged
Interrupt handling
Interrupts are a sub-class of exception
Automatic save and restore of processor registers (xPSR, PC, LR, R12, R3-R0)
Allows handler to be written entirely in C

External Interrupts
External Interrupts handled by Nested Vectored Interrupt Controller (NVIC)
Tightly coupled with processor core
One Non-Maskable Interrupt (NMI) supported
Number of external interrupts is implementation-defined
ARMv7-M supports up to 496 interrupts
INTNMI
INTISR[0]
NVIC

Cortex-Mx
INTISR[N] Processor Core
Cortex-Mx Integration Layer

Exception Handling Example
Higher Priority
IRQ1
IRQ2
IRQ3
Base CPU
Time
Core Execution Foreground ISR2 ISR1 ISR2 ISR3 Foreground
(ISR 2 resumes)

Vector Table for ARMv7-M
First entry contains initial Main SP Address Vector #
0x40 + 4*N External N 16 + N
All other entries are addresses for
exception handlers
Must always have LSBit = 1 (for Thumb) 0x40 External 0 16
0x3C SysTick 15
Table has up to 496 external interrupts 0x38 PendSV 14
Implementation-defined
Maximum table size is 2048 bytes 0x34 Reserved 13
0x30 Debug Monitor 12
Table may be relocated 0x2C SVC 11
Use Vector Table Offset Register 0x1C to 0x28 Reserved (x4) 7-10
Still require minimal table entries at 0x0 for
booting the core 0x18 Usage Fault 6
0x14 Bus Fault 5
Each exception has a vector number 0x10 Mem Manage Fault 4
Used in Interrupt Control and State Register to
indicate the active or pending exception type 0x0C Hard Fault 3
0x08 NMI 2
Table can be generated using C code 0x04 Reset 1
Example provided later 0x00 Initial Main SP N/A

Reset Behavior
Main
5
4
Reset Handler
Reset Handler Vector

1 0x04 Initial value of MSP r13 (MSP)
0x00 2
1. A reset occurs (Reset input was asserted)

2. Load MSP (Main Stack Pointer) register initial value from address 0x00
3. Load reset handler vector address from address 0x04
4. Reset handler executes in Thread Mode
5. Optional: Reset handler branches to the main program

Exception Behaviour
Main
4
3
1
Exception Handler
Exception Vector
1. Exception occurs
Current instruction stream stops
Processor accesses vector table
2. Vector address for the exception loaded from the vector table
3. Exception handler executes in Handler Mode
4. Exception handler returns to main

Interrupt Service Routine Entry
When receiving an interrupt the processor will finish the current instruction for
most instructions
To minimize interrupt latency, the processor can take an interrupt during the execution of a
multi-cycle instruction - see next slide
Processor state automatically saved to the current stack

8 registers are pushed: PC, R0-R3, R12, LR, xPSR
Follows ARM Architecture Procedure Calling Standard (AAPCS)
During (or after) state saving the address of the ISR is read from the Vector Table
Link Register is modified for interrupt return
First instruction of ISR executed

For Cortex-M3 or Cortex-M4 the total latency is normally 12 cycles, however, interrupt late-
arrival and interrupt tail-chaining can improve IRQ latency
ISR executes from Handler mode with Main stack

Returning From Interrupt
Can return from interrupt with the following instructions when the PC is
loaded with magic value of 0xFFFF_FFFX (same format as EXC_RETURN)
LDR PC, ..
LDM/POP which includes loading the PC
BX LR (most common)
If no interrupts are pending, foreground state is restored

Stack and state specified by EXC_RETURN is used
Context restore on Cortex-M3 and Cortex-M4 requires 10 cycles
If other interrupts are pending, the highest priority may be serviced

Serviced if interrupt priority is higher than the foregrounds base priority
Process is called Tail-Chaining as foreground state is not yet restored
Latency for servicing new interrupt is only 6 cycles on M3/M4 (state already saved)
If state restore is interrupted, it is abandoned

New ISR executed without state saving (original state still intact and valid)
Must still fetch new vector and refill pipeline (6-cycle latency on M3/M4)
Vector Table in C
typedef void(* const ExecFuncPtr)(void) __irq;
#pragma arm section rodata="exceptions_area
ExecFuncPtr exception_table[] = {
(ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, /* Initial SP */
(ExecFuncPtr)__main, /* Initial PC */
NMIException,
The vector table at address
HardFaultException,
0x0 is minimally required to
MemManageException,
have 4 values: stack top,
BusFaultException,
reset routine location,
UsageFaultException,
NMI ISR location,
0, 0, 0, 0, /* Reserved */
HardFault ISR location
SVCHandler,
DebugMonitor, The SVCall ISR
0, /* Reserved */ location must be
PendSVC, populated if the
SysTickHandler SVC instruction will
/* Configurable interrupts start here...*/ Once interrupts be used
}; are enabled, the
#pragma arm section vector table
(whether at 0 or in
SRAM) must then
have pointers to all
enabled (by mask)
exceptions
Vector Table in Assembly
PRESERVE8
THUMB
IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit||
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack

DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MemManage Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0, 0, 0, 0, ; Reserved x4
DCD SVC_Handler, ; SVCall Handler
DCD Debug_Monitor ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External vectors start here

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Processor Memory Map
External Private Peripheral Bus
E00F_FFFF
ROM Table
E00F_F000
UNUSED FFFF_FFFF
E004_2000 512MB System (XN)
ETM
E004_1000 E000_0000
TPIU
E004_0000
1GB External
E003_FFFF Peripheral
RESERVED
E000_F000
NVIC A000_0000
E000_E000
RESERVED
E000_3000
FPB 1 GB External
E000_2000
DWT SRAM
E000_1000
ITM
E000_0000 6000_0000
Internal Private Peripheral Bus
512MB Peripheral
4000_0000
512MB SRAM
2000_0000
512MB Code
0000_0000

Memory Types and Properties
There are 3 different memory types:
Normal, Device and Strongly Ordered
Normal memory is the most flexible memory type:

Suitable for different types of memory, for example, ROM, RAM, Flash and SDRAM
Accesses may be restarted
Caches and Write Buffers are permitted to work alongside Normal memory
Device memory is suitable for peripherals and I/O devices

Caches are not permitted, but write buffers are still supported
Unaligned accesses are unpredictable
Accesses must not be restarted
Load/store multiple instructions should not be used to access Device memory
Strongly ordered memory is similar to Device memory

Buffers are not supported and the PPB is marked Strongly Ordered

System Control Block
Memory mapped space containing registers to configure, control, and deal
with interrupts, exceptions, and debug
Replaces co-processor #15 in older ARM cores
Address Type Reset Value Function
0xE000E000 Read/Write 0x00000000 Master Control register - RESERVED
0xE000E004 Read Only IMP DEFINED Interrupt Controller Type Register
0xE000ED00 Read Only IMP DEFINED CPUID Base Register
0xE000ED04 Read/Write 0x00000000 Interrupt Control State Register
0xE000ED08 Read/Write 0x00000000 Vector Table Offset Register
0xE000ED0C Read/Write Bits[10:8] = 000 Application Interrupt/Reset Control

Register

More SCB Registers
Address Type Reset Value Function
0xE000ED10 Read/Write 0x00000000 System Control Register
0xE000ED14 Read/Write 0x00000000 Configuration Control Register
0xE000ED18 Read/Write 0x00000000 System Handlers 4-7 Priority Register
0xE000ED1C Read/Write 0x00000000 System Handlers 8-11 Priority Register
0xE000ED20 Read/Write 0x00000000 System Handlers 12-15 Priority Register
0xE000ED24 Read/Write 0x00000000 System Handler Control and State Register
0xE000ED28 Read/Write n/a - status Configurable Fault Status Registers (3)
0xE000ED2C Read/Write n/a - status HardFault Status Register
0xE000ED30 Read/Write n/a - status DebugFault Status Register
0xE000ED34 Read/Write Unpredictable MemManage Address Register
0xE000ED38 Read/Write Unpredictable BusFault Address Register
0xE000ED3C Read/Write Unpredictable Auxiliary Fault Status Register (vendor specific)
0xE000EF00 Write Only Software Trigger Interrupt Register

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Cortex-M4
ARMv7E-M Architecture
Thumb-2 only
DSP extensions
Optional FPU (Cortex-M4F)
Otherwise, same as Cortex-M3
Implements full Thumb-2

instruction set
Saturated math (e.g. QADD)
Packing and unpacking (e.g. UXTB)
Signed multiply (e.g. SMULTB)
SIMD (e.g. ADD8)
Cortex M3 Total
60k* Gates
Cortex-M4F Floating Point Registers
FPU provides a further 32 single-precision registers
Can be viewed as either
32 x 32-bit registers S0
D0
16 x 64-bit doubleword registers S1
Any combination of the above S2
D1
S3
S4
D2
S5
S6
D3
S7
~
~ ~
~ ~
~ ~
~
S28
D14
S29
S30
D15
S31

Binary Upwards Compatibility
ARMv7-M
Architecture
ARMv6-M
Architecture

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

Example ARM-based system
ARM core deeply embedded within an
SoC
Clocks and DMA
External debug and trace via JTAG or Reset Controller Port
CoreSight interface
Design can have both external and
ARM
FLASH
internal memories Processor
External
Memory
AMBA AXI
Varying width, speed and size core Interface
depending on system requirements DEBUG
Can include ARM licensed CoreLink nIRQ

On chip
SDRAM
nFIQ
peripherals memory
CoreLink
Interrupt controller, since core only has Interrupt
Controller
two interrupt sources APB
Bridge
AMBA APB
Other
Other peripherals and interfaces CoreLink
Can include on-chip memory from Peripherals
ARM Artisan Physical IP Libraries Custom

ARM based
Elements connected using AMBA Peripherals
SoC
(Advanced Microcontroller Bus
Architecture)

An Example AMBA System
High Performance
APB
ARM processor UART
High
Bandwidth AHB Timer
APB
External
Bridge
Memory Keypad
Interface
High-bandwidth DMA PIO

on-chip RAM Bus Master
Low Power
Non-pipelined
High Performance Simple Interface
Pipelined
Burst Support
Multiple Bus Masters

AHB Structure
Arbiter
HADDR
HADDR HWDATA Slave
Master HWDATA
#1
HRDATA
#1
HRDATA
Address/Control
Slave
#2
Master
#2
Write Data
Slave
Read Data #3
Master
#3
Slave
#4
Decoder

AXI Multi-Master System Design
ARM Master 2
Inter-connection architecture
Slave Slave Slave Slave

#1 #2 #3 #4
Master interface
Slave interface

Agenda
Introduction
Programmers Model
Memory Systems
Programmers Model
Memory Systems
ARM System Design

ARM Software Development Tools
Software Tools JTAG Debug and Trace Development Platforms

DS-5 DSTREAM Fast Models
Application Edition Versatile Platform
Linux Edition baseboards
Professional Edition
MDK: Keil ULINK Keil MCU development

Microcontroller boards
Development Kit Keil Vision simulator

DS-5 Professional at a Glance
Integrated solution, professionally supported and maintained
End-to-end development, from SoC bring-up to application debug
Powerful ARM compiler

Best code size and performance DS-5
Eclipse
Compiler
Intuitive DS-5 debugger IDE Debugger Streamline
Flexible graphical user interface Device Configuration Database
DSTREAM probe with 4GB trace buffer
Simulation Hardware Debug
Fast SoC simulation models

Develop in a controlled environment
Examples and applications
Streamline performance analyzer

System-wide analysis of Linux
and Android systems

Development Suite: MDK
Low cost tools for ARM7, ARM9, Cortex-M and Cortex-R4 MCUs
Extensive device support for many devices
Core and peripheral simulation
Flash support
Microcontroller Development Kit (MDK)
IDE, optimized run-time library, KEIL RTX RTOS
ARM Compiler
Realtime trace (for Cortex-M3 and Cortex-M4 based devices)
Real-Time Library
KEIL RTX RTOS + Source Code
TCP networking suit, Flash File System, CAN Driver Library, USB Device Interface
Debug Hardware
Evaluation boards
Separate support channel

See www.keil.com

GNU Tools and Linux
GNU/GCC Tools Support
ARM works with CodeSourcery to keep the GNU toolchain current with the latest
ARM processors
Linux Support
Pre-built Linux images are available for ARM hardware platforms
DS-5 accepts kernel images built with the GNU toolchain
Can also debug applications or loadable kernel modules
RVCT can be used to build Linux applications or libraries
Giving performance benefits
ARM does not provide technical support for the GNU toolchain, or Linux
kernel/driver development

ARM University
Program
August 2012


ARM Processors and Architectures - Uni Program

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ARM Processors and

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Company headquarters in Cambridge, UK

Best known for its range of RISC processor cores designs

ARM does not manufacture silicon

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Connect, Collaborate, Create accelerating innovation

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Note that implementations of the same architecture can be different

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Real-time profile (ARMv7-R)

Microcontroller profile (ARMv7-M, ARMv7E-M, ARMv6-M)

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Real-time profile (ARMv7-R)

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ARM cores implement two basic instruction sets

Depending on the core, may also implement other instruction sets

Entered when a high priority (fast) interrupt is

IRQ Entered when a normal priority interrupt is raised

Undef Used to handle undefined instructions

Privileged mode using the same registers as User

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Current mode Banked out registers

N Z C V Q [de] J GE[3:0] IT[abc] E A I F T mode

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Cores are either in ARM state or Thumb state

The architecture allows programmers and compilation tools to reduce

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comparison CMN CMP TST TEQ

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Causes an SVC exception

By using the SVC mechanism, an operating system can implement a set

Thumb version is unconditional

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Note that v7-M and v6-M exception model is different

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2. Change processor status for exception

Mode field bits

ARM or Thumb state

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NEON instructions perform Packed SIMD processing

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Two different views of the NEON registers

Enables register trade-offs D2

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3. Map each unrolled operation onto + + + + +

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The memory type controls the following:

There are 3 mutually exclusive memory types:

Normal and Device memory allow additional attributes for specifying

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Typical memory system can have multiple levels of cache