Digital IC Design

Faculty-in-charge: Dr. Sitangshu Bhattacharya

Department of ECE
Indian Institute of Information Technology-Allahabad
Room No. 2221, CC-I
Telephone: 2131
Email: sitangshu@iiita.ac.in
Digital IC Design

Contents:

o MOS Transistor: Structure, External Bias,
Operation, Current-Voltage Characteristics,
Capacitances, Small Geometry Scaling
o MOS Inverters: Resistive Load Inverter, n-type
MOSFET load inverter, CMOS inverter
o Switching Characteristics and Interconnect
Effects: Delay Time and constraints, Interconnect
parasitics, Interconnect delay calculation, Switching
power dissipation of CMOS inverters
o Dynamic Logic Circuits Pass transistors, Voltage
Bootstrapping, Synchronous Dynamic Circuit
Testing, Dynamic CMOS Circuit Techniques, High
performance Dynamic CMOS circuits
o Semiconductor Memories DRAM, SRAM, Non-
volatile, Flash Memory, FRAM
o Low Power CMOS Logic Circuits Low Power
Design Switching Activity, Switched Capacitance,
Adiabatic Logic Circuits

o Combinational MOS Logic Depletion Logic o BiCMOS Logic Circuits BJT, Dynamic behavior,
Circuits with nMOS loads, CMOS logic circuits, BiCMOS static behavior Switching Delay
CMOS transmission gates
o Chip I/O Circuits ESD protection, Output Circuit
o Sequential MOS Logic Bistable elements, SR Noise, On Chip Clock Generation and Distribution,
Latch, Clocked Latch with FF circuits, CMOS D- Latchup and its prevention
latch and Edge Triggered FFs
Reading Materials:
1. CMOS Digital Integrated Circuits Analysis and Design By S-Mo Kang and Y Leblebici
2. Digital Integrated Circuits: Analysis and Design By John E. Ayers
3. Digital Integrated Circuits: A Design Perspective By Anantha P. Chandrakasan,
Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017 Borivoje Nikolic, and Jan M. Rabaey
Digital IC Design

Sequential MOS Logic

Sequential MOS Logic

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Input of 2 is the output of 1 and input of 1 is output of 2

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Voltage transfer curve of gate 1

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Voltage transfer curve of gate 2

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Voltage transfer curve of gate 1 & 2

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

There are 3 intersection points out of which two are stable (thus bistable) and 1 is unstable.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

There are 3 intersection points out of which two are stable (thus bistable) and 1 is unstable.

Inverter gain (i.e. slope) at these two stable points is less than unity.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

There are 3 intersection points out of which two are stable (thus bistable) and 1 is unstable.

Inverter gain (i.e. slope) at these two stable points is less than unity.

To go from one stable state to another, large voltage should be applied (that make the loop gain infinity).

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

If the operating point is at the third (unstable) intersection, the large gain at this point will transfer the
operating point to any one of the stable state.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

If the operating point is at the third (unstable) intersection, the large gain at this point will transfer the
operating point to any one of the stable state.

Examples: All basic latch, FFs, registers, memory falls under bistable.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

If the operating point is at the third (unstable) intersection, the large gain at this point will transfer the
operating point to any one of the stable state.

Examples: All basic latch, FFs, registers, memory falls under bistable.
Example: Ring oscillator falls under monostable.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

The circuit preserves the state in one of the two stable voltages unless an external voltage is supplied

Memory

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Cross-coupled CMOS inverter:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Cross-coupled CMOS inverter:

All the four transistors are in saturation at the unstable point with a maximum loop gain.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Cross-coupled CMOS inverter:

All the four transistors are in saturation at the unstable point with a maximum loop gain.

If the initial operating condition is set at this point, any small voltage perturbation will cause significant
changes in the operating modes of the transistors.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable

Cross-coupled CMOS inverter:

All the four transistors are in saturation at the unstable point with a maximum loop gain.

If the initial operating condition is set at this point, any small voltage perturbation will cause significant
changes in the operating modes of the transistors.

Thus, we expect the output voltages of the two inverters to diverge and eventually settle at VOH and VOL.
The direction to which it will go, depends on the initial perturbation polarity.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Let both the c-c transistors be operated at saturation (unstable): v01 = v02 = vth (i.e, switch threshold)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Let both the c-c transistors be operated at saturation (unstable): v01 = v02 = vth (i.e, switch threshold)

To bypass stray capacitances, assume Cg >> Cd

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Let both the c-c transistors be operated at saturation (unstable): v01 = v02 = vth (i.e, switch threshold)

To bypass stray capacitances, assume Cg >> Cd

Small signal drain currents: (these are the changes)

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Let both the c-c transistors be operated at saturation (unstable): v01 = v02 = vth (i.e, switch threshold)

To bypass stray capacitances, assume Cg >> Cd

Small signal drain currents: (these are the changes)

Small signal gate voltages of both inverters in terms of charges:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Let both the c-c transistors be operated at saturation (unstable): v01 = v02 = vth (i.e, switch threshold)

To bypass stray capacitances, assume Cg >> Cd

Small signal drain currents: (these are the changes)

Small signal gate voltages of both inverters in terms of charges:

This leads to the change in currents as:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Let both the c-c transistors be operated at saturation (unstable): v01 = v02 = vth (i.e, switch threshold)

To bypass stray capacitances, assume Cg >> Cd

Small signal drain currents: (these are the changes)

Small signal gate voltages of both inverters in terms of charges:

This leads to the change in currents as:

Note that these are coupled equations.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017
Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

This can be written in terms of charges as

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

This can be written in terms of charges as

One can finally write these as:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

This can be written in terms of charges as

One can finally write these as:

With the initial condition: and

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

This can be written in terms of charges as

One can finally write these as:

With the initial condition: and

This is an exponential solution answer to this PDE

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Since vg1 = v02 and vg2 = v01:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

Since vg1 = v02 and vg2 = v01: Note solutions are not coupled!

For large values of time,

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Small signal analysis: Transients

For large values of time,

Depending on the polarity of small perturbing potential, the output

voltage of both inverters will diverge from their initial value vth to
either VOL or VOH .: Charge conservation principle.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Bistable-Transient while settling

When the bistable settles from its unstable position: You may think a signal travels around the loop
several times

with

If the signal loops n times during a time interval T, signal travels through a cascaded chain of 2n
inverters

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NOR based SR latch

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NOR based SR latch

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NOR based SR latch

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NOR based SR latch : switching times:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NOR based SR latch : switching times:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NOR based SR latch : Depletion Load:

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NAND based SR latch :

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : SR latch

NAND based SR latch : Depletion Load

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked SR latch

AOI based implementation

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked JK latch

CMOS AOI based implementation

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked D latch

CMOS based implementation

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked D latch

CMOS based implementation

When the input CLK is high, CLK in loop is low

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked D latch

CMOS based implementation

When the input CLK is high, CLK in loop is low

During this, the data can enter and goes

through the double inverter.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked D latch

CMOS based implementation

When the input CLK is high, CLK in loop is low

During this, the data can enter and goes

through the double inverter.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked D latch

CMOS based implementation

When the input CLK is high, CLK in loop is low

During this, the data can enter and goes

through the double inverter.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked D latch

CMOS based implementation

When the input CLK is high, CLK in loop is low

During this, the data can enter and goes

through the double inverter.

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017

Digital IC Design

Sequential MOS Logic : Clocked D latch: Metastability problem

Faculty-in-charge: Dr. Sitangshu Bhattacharya 2017