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Memory Management Strategies

CS2203: Operating System


Qasim Tasneem

Center For Advanced Studies In Engineering


Islamabad, Pakistan
Reading and Credit

Readings for these lecture notes: Silberschatz, Galvin,


and Gagne, Chapter 8

These notes contain material from Silberschatz,


Galvin, and Gagne (2008)
Objectives

To provide a detailed description of various ways of organizing


memory hardware

To discuss various memory-management techniques, including


paging and segmentation
Outline

Introduction

Dynamic Loading and Linking

Swapping

Contiguous Memory Allocation

Fragmentation

Paging

Segmentation

Introduction
Introduction

Program must be brought (from disk) into memory

Main memory and registers are only storage CPU can access directly

Register access in one CPU clock (or less)

Main memory access may take many cycles (transaction on memory


bus)

Cache sits between main memory and CPU registers

Protection of memory required to ensure correct operation


Background
Main Memory

CPU cache
instructions
Registers
data Process
program image
in memory

Operating
System
Disk
Program addresses and memory
When code is generated (or
assembly program is written) we func variable
use memory addresses for
variables, functions and func variable
branching/jumping.
func variable

main
Those addresses can be physical or
logical memory addresses.
program

In very early systems they are just


physical memory addresses.
A program has to be loaded to
that address to run.
No relocation
Program addresses and memory
physical addresses
RAM of RAM
Assume they are physical addresses
44
40
Program 36
32
Add 12 28
Mov 8 24
4 20
Jump 8 0 16
Add 12
Mov 8
4
Jump 8 0
Program addresses and memory
physical addresses
RAM of RAM

44
40
36
32
Cmp 28

Program 2
Sub 24
Program 1 Program 2
20
Jump 12 16
Add 12 Cmp 12 Program 1 Add 12
Mov 8 Sub 8
Mov 8
4 4
4
Jump 8 0 Jump 12 0
Jump 8 0
Logical address space concept
We need logical address space RAM
concept, that is different that phy_max
the physical RAM (main
memory) addresses.

A program uses logical logic_max limit Program


addresses.

logical base
address Program
Set of logical addresses used by
the program is its logical space
address space
Logical address space can be, 0
for example, [0, max_address]
0
Logical address space has to be
mapped somewhere in physical
memory
Base and Limit Registers
A pair of base and limit registers define the address space of a process

A process should be accessing


and using that range.

Protection provided in this way.

Each physical address should be in


range [base, base+limit]
Base and Limit Registers (Cont.)
Multistep Processing of a User
Program
Address Binding

Process access instructions and data from memory

Instructions and data are accessed through address

Source code contains symbolic addresses e.g., count, name etc.

A compiler typically binds symbolic address to relocatable


address e.g., 14 bytes from the beginning of this module.
Address Binding (Cont.)

Address binding of instructions and data to memory addresses can


happen at three different stages:
Compile time: If memory location to allocate is known a priori,
absolute code can be generated. The MS-DOS .COM-format programs
are bound at compile time.
Load time: Must generate relocatable code if memory location is not
known at compile time
Execution time: If the process can be moved during its execution
from one memory segment to another, then binding delayed until run
time. Most general-purpose operating systems use this method
Logical vs. Physical Address Space

The concept of a logical address space that is bound to a


separate physical address space is central to proper memory
management
Logical addressgenerated by the CPU; also referred to as virtual
address
Physical addressaddress seen by the memory unit

Logical and physical addresses are the same in compile-time


and load-time address-binding schemes; logical (virtual) and
physical addresses differ in execution-time address-binding
scheme
Logical and physical addresses
CPU Main Memory (RAM)
base limit 60
24 32 56
int x 52
PC int y; 48

physical addresses
M[28+base] cmp .. 44
IR mov r1, M[28] mov r1, M[28] 40
M[28+24] mov r2, M[24] 36
M[52] add r1, r2, r3
a relocatable program 32
jmp 16 28
28 int x mov .. 24
24 int y;
logical addresses

20
20 cmp ..
16
16 mov r1, M[28]
12
12 mov r2, M[24]
08
08 add r1, r2, r3
04
04 jmp 16
00
00 mov ..
Memory-Management Unit (MMU)

Hardware device that maps virtual to physical address

In MMU scheme, the value in the relocation register is added to


every address generated by a user process at the time it is sent
to memory

The user program deals with logical addresses; it never sees the
real physical addresses
Dynamic Relocation
Dynamic relocation using a relocation register
Dynamic Loading

Routine is not loaded until it is called

Better memory-space utilization; unused routine is never


loaded

Useful when large amounts of code are needed to handle


infrequently occurring cases

No special support from the operating system is required


implemented through program design
Dynamic Linking

Linking postponed until execution time

Small piece of code, stub, used to locate the appropriate memory-


resident library routine
Stub replaces itself with the address of the routine, and executes the
routine
Operating system needed to check if routine is in processes memory
address
Dynamic linking is particularly useful for libraries

System also known as shared libraries



Swapping
Swapping

A process can be swapped temporarily out of memory to a backing


store, and then brought back into memory for continued execution

Backing storefast disk large enough to accommodate copies of


all memory images for all users; must provide direct access to
these memory images

Roll out, roll inswapping variant used for priority-based


scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and execute
Swapping (Cont.)

Major part of swap time is transfer time; total transfer time is


directly proportional to the amount of memory swapped

Schematic View of Swapping



Contiguous Memory Allocation
Contiguous Memory Allocation

Main memory divided into two parts:

Resident operating system; held in low memory part

User processes; held in high memory part


Contiguous Memory Allocation (Cont.)
Multiple-partition allocation

Hole: block of available memory; holes of various size are


scattered throughout memory

When a process arrives, it is allocated memory from a hole large


enough to accommodate it

Operating system maintains information about:


allocated partitions
free partitions (hole)
Contiguous Memory Allocation (Cont.)

How to satisfy a request of size n from a list of free holes


First-fit: Allocate the first hole that is big enough

Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size
Produces the smallest leftover hole

Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

Fragmentation
Fragmentation

External Fragmentation:
total memory space exists to satisfy a request, but it is not
contiguous

Internal Fragmentation:
Suppose physical memory is divided into fix block sizes then
allocated memory may be slightly larger than requested memory
The different between allocated and required is called internal
fragmentation
Fragmentation (Cont.)

Reduce external fragmentation by compaction

Compaction: shuffle memory contents to place all free memory


together in one large block

Compaction is possible only if relocation is dynamic, and is done


at execution time

Paging
Paging
Paging permits the physical address space of a process to be noncontiguous. Basic
method for implementing paging involves:

Divide physical memory into fixed-sized blocks called frames (size is power of 2,
between 512 bytes and 8,192 bytes)

Divide logical memory into blocks of same size called pages

Keep track of all free frames

To run a program of size n pages, need to find n free frames and load program

Set up a page table to translate logical to physical addresses

Internal fragmentation is possible


Paging (Cont.)

Every address generated by the CPU is divided into:


Page number (p)used as an index into a page table which
contains base address of each page in physical memory

Page offset (d)combined with base address to define the


physical memory address that is sent to the memory unit
Paging (Cont.)

Paging Hardware
Paging (Cont.)

Paging Model of Logical and Physical Memory


Paging (Cont.)

Identify the physical address of g and o

Paging Example: 32-byte memory and 4-byte pages


Paging (Cont.)

Before allocation After allocation



Segmentation
Segmentation

Programs need to share data on a controlled basis. For example:


Two processes may wish to share part of their data
Process should be able to execute its code, but not its data

Process should share part of memory with other processes, but not
all of memory
Some memory may need to be exported read-only, other memory
exported read/write

Segments:
Program's memory is structured as a set of segments

Each segment is a variable-sized chunk of memory

Source: http://people.csail.mit.edu/rinard/osnotes/h15.html
Segmentation (Cont.)

A program is a collection of segments


A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Segmentation (Cont.)

User View of Program


Segmentation (Cont.)

Logical View of Segmentation


Segmentation (Cont.)

Logical address consists of a two tuple:


<segment-number, offset>,

Segment tablemaps two-dimensional physical addresses; each table entry


has:
basecontains the starting physical address where the segments reside in
memory
limitspecifies the length of the segment

Segment-table base register (STBR) points to the segment tables location in


memory
Segment-table length register (STLR) indicates number of segments used by
a program;
segment number s is legal if s < STLR
Segmentation (Cont.)

Example of Segmentation
Suggested Reading

Section 8.5 (Structure of the Page Table) of the text book

Section 8.7 (Example: The Intel Pentium) of the text book

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