Ahmed Faraz

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Definition and Characteristics
Superscalar processing is the ability to initiate multiple
instructions during the same clock cycle.
A typical Superscalar processor fetches and decodes
the incoming instruction stream several instructions
at a time.
Superscalar architecture exploit the potential of
ILP(Instruction Level Parallelism).

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 Fetching and dispatching two instructions per cycle
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Uninterrupted stream of
instructions
The outcomes of conditional branch instructions are
usually predicted in advance to ensure uninterrupted
stream of instructions
Instructions are initiated for execution in parallel
based on the availability of operand data, rather than
their original program sequence. This is referred to as
dynamic instruction scheduling.
Upon completion instruction results are resequenced
in the original order.

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 Superscalar Execution Example

- With Register Renaming for WAR

and WAW dependencies.

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.
Register Renaming Example
WAR dependency exist between LD r7,(r3) and SUB r3, r12,r11 instructions

With Register Renaming, the first write to r3 maps to hw3,while the second write
maps to hw20.This converts four instruction dependency chain into 2 two instructions
chains, which can then be executed in parallel if the processor allows out of order
execution.

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 Hardware Organization of a superscalar processor

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 CONCLUSION
It thereby allows faster CPU throughput than would
otherwise be possible at the same clock rate.
All general-purpose CPUs developed since about 1998 are
superscalar.

The major problem of executing multiple instructions in a

scalar program is the handling of data dependencies. If
data dependencies are not effectively handled, it is difficult
to achieve an execution rate of more than one instruction
per clock cycle.

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 References
THE MICRO ARCHITECTURE OF SUPERSCALAR PROCESSORS BY
JAMES E. SMITH, MEMBER, IEEE, AND GURINDAR S. SOHI, SENIOR MEMBER, IEEE

http://en.wikipedia.org/wiki/Superscalar
http://www.seas.gwu.edu/~bhagiweb/cs211/lectures/superscalar.pdf
LIMITATION OF SUPERSCALAR MICROPROCESSOR PERFORMANCE
THANG TRAN ,ADVANCED MICRO DEVICES, INC. AUSTIN, TEXAS 78741 AND CHUAN-LIN WU,DEPARTMENT OF ELECTRICAL
AND COMPUTER ENGINEERING

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