Transistor Technologies

Voltage Levels

The binary values 0 and 1 can be represented as

levels of current or of voltage voltage is most
common Voltage

VDD
Positive logic system associates
1 with high and 0 with low Logic value 1

V1,min
Max voltage is VDD (or VCC)
5V for TTL Undefined
Much smaller (1.0 V) for ASICs
V0,max

Min voltage is VSS (or Gnd) Logic value 0

Typically 0V
VSS (Gnd)
 Logic Ranges

Typically V0,max = 0.4VDD and V1,min = 0.6VDD

Voltage

5V VDD

Logic value 1

3V V1,min

Undefined

2V V0,max

Logic value 0

VSS (Gnd)
 Transistors Switches

Gates are built from transistors

MOSFETS metal oxide semiconductor field-effect

transistors
Most popular type of transistors

Two types of MOSFETS

NMOS n channel
PMOS p channel
 NMOS Transistors

4 electrical terminals
Source Gate
Drain
Gate
Source Drain
Substrate
Substrate (Body)
Connected to Gnd

Source and drain are only different in their

interpretation
Terminal with lower voltage is the source (by convention)
VG
Simplified symbol omits the substrate
VS VD
 NMOS Behavior

When Gate (VG) is high (i.e. 1) the NMOS transistor

acts as a closed switch
When VG = 0, the NMOS transistor is an open switch

VG

VS VD

VG = "low" VG = "high"
 PMOS Transistors

Same 4 electrical terminals

Source Gate
Drain
Gate
Drain Source
Substrate VDD
Connected to VDD Substrate (Body)

Again, source and drain are only different in their

interpretation
Terminal with higher voltage is the source (by convention)
VG
Simplified symbol omits the substrate
VS VD
 PMOS Behavior

When Gate (VG) is low (i.e. 0) the PMOS transistor

acts as a closed switch
When VG = 1, the PMOS transistor is an open switch

VG

VS VD

VG = "high" VG = "low"
 Building an Inverter

When Vx = 0 V (NMOS transistor is an open switch),

current flows thru the resistor R, and Vf = 5 V

R
+
5V
- Vf
VDD
Vx

Vf

Simplified circuit diagram Vx

 NOT Gates

When Vx = 5 V (NMOS transistor is a closed switch),

the transistor pulls Vf to Gnd (i.e. 0 V) VDD

Vf is the complement of Vx R

Vf
Common symbols used for this Vx

x f x f

required to limit current

flow when Vx = 5 V
Note: 1 NMOS + 1 resistor (V = I * R)
 NAND Gates
x1 x2 f
Truth table for NAND is
0 0 1
VDD 0 1 1
1 0 1
1 1 0

Vf
When x1 = x2 = 1, both NMOS transistors
Vx
1
are closed and Vf is pulled down to Gnd (0)

Vx
2 x1 x1
f f
x2 x2

Note: 2 NMOS + 1 resistor

 NOR Gates
x1 x2 f
Truth table for NOR is
0 0 1
0 1 0
1 0 0
1 1 0

When x1 = x2 = 0, both NMOS transistors

are open and Vf is pulled up to VDD (1)

Note: 2 NMOS + 1 resistor

 AND Gates
x1 x2 f
Truth table for AND is
0 0 0
VDD VDD
0 1 1
1 0 1
1 1 1
Vf

A
Vx1
This is a NAND followed by a NOT!

Vx2

Note: 3 NMOS + 2 resistors

 OR Gates
x1 x2 f
Truth table for OR is
0 0 0
0 1 0
1 0 0
1 1 1

This is a NOR followed by a NOT!

Note: 3 NMOS + 2 resistors

 General NMOS Circuits

The general structure of an NMOS circuit consists of

Network of NMOS transistors to pull down the output
voltage (pull-down network PDN)
A resistor that acts as a pull up device
VDD

Vf
operates to pull Vf
Vx
1
Pull-down network
to Gnd
(PDN)
Vx
n
 CMOS Circuits

Replacing the pull-up resister with a pull-up network

(PUN) leads to CMOS technology
CMOS complementary metal oxide semiconductor
VDD

Pull-up network
(PUN) PMOS transistors

Vf

Vx
1
Pull-down network
(PDN)
NMOS transistors
Vx
n
 CMOS Technology

For any input combination, either:

The PDN pulls Vf down to Gnd, or
The PUN pulls Vf up to VDD

The PUN and PDN have the same number of

transistors

The PUN and PDN are duals of each other

NMOS transistors in series in the PDN PMOS transistor
in parallel in the PUN, and vice versa
Complementary MOS complementary means duals
 CMOS Inverter

When Vx = 0 V, T1 is on and T2 is off Vf = 5 V

When Vx = 5 V, T1 is off and T2 is on Vf = 0 V

No (actually, very little) current flows! VDD

Very little power is dissipated in steady state
V = IR and P = IV P = I2R
T1
Low power is reason for CMOS
popularity in current technology V Vf
x

T2
Current does not flow (to any significant
degree) in any CMOS implementation
 CMOS NAND & NOR

NAND technology NOR technology

 CMOS AND

CMOS NAND followed by a CMOS NOT

VDD VDD

Vf

Vx
1

Vx
2
 Complex CMOS Circuits

The PUN is responsible for dictating when VDD

Vf = 1

Suppose you want to implement

f=x1+x2x3 in CMOS
The PUN implements this
Vf

Note that f=x1(x2+x3) is Vx

1

implemented by the PDN

Vx
2

Vx
3
 Another Complex CMOS Circuit
VDD

f=x1+(x2+x3)x4
The PUN implements this

f=x1(x2x3+x4)
The PDN implements this
Vf

Vx
1

Vx
2

Vx
3

Vx
4
MOSFET Circuit Fabrication
 MOSFET Fabrication (NMOS)

Type n areas have an excess of negative charge

Type p areas have an excess of positive charge
When the gate voltage = 0, no current flows
Glass layer
VG = 0 V that insulates
SiO2
the gate from
the substrate

VS = 0 V
VD

++++++++++ ++++++
+++++++++ ++++++
++++++ ++++++
++++++ ++++++
++++++
+++++++++++ ++++++ +++++++++++
+++++++++ Substrate (type +++++++++
p)

Source (type n) Drain (type n)

 NMOS Gate in Action

When the gate voltage = 5 V, free electrons are

attracted to the gate and creates a channel from
source to drain
Channel size is dictated by length L and width W of the
transistor VDD

V = 5V
G
SiO
2

V = 0V
S V = 0V
D
++++++ ++++ +++ ++++++
++++++ ++++++
+++++++++++ +++++++++++++++++
+++++++++ +++++++++ ++++++++++

Channel (type n)
 Current-Voltage in NMOS

Let VGS = gate to source voltage (potential difference)

When VGS exceeds some threshold VT, then the

NMOS gate closes
n type channel is created in the substrate
No current flows thru the gate since the SiO2 layer prevents it

Current ID may flow from drain to source

ID depends on the voltage level applied across the channel
from drain to source (VDS)
 Triode vs Saturation Regions

For a fixed value of VGS, ID varies approximately

linearly with VDS as long as 0<VDS<(VGSVT)
i.e., for small range of voltages, the current increases linearly
W 1 2
I D kn ' [(VGS VT )VDS VDS ]
L 2
Beyond this range,
saturation occurs ID
1 W
I D k n ' (VGS VT ) 2 Triode Saturation
2 L

Process transconductance
parameter: constant that depends
on technology in use

0 VGS VT VDS
 Example Current Calculation (1)

Let kn' = 60A/V2, W/L = 2.0m/0.5m, VS = 0 V,

VG = 5 V, and VT = 1V

If VD = 2.5 V, then VD < VGS VT = 4 V, so the

transistor is in the triode region and ID = 1.65 mA
ID

Triode Saturation
W 1 2
I D k n ' [(VGS VT )VDS VDS ]
L 2
2 1 2
60 [(5 1)2.5 2.5 ] 1.65 mA
0.5 2

0 VGS VT VDS
 Example Current Calculation (2)

Let kn' = 60A/V2, W/L = 2.0m/0.5m, VS = 0 V,

VG = 5 V, and VT = 1V

If VD = 5 V, then VD > VGS VT = 4 V, so the transistor

is in the saturation region and ID = 1.9 mA
ID

1 W Triode Saturation
I D k n ' (VGS VT ) 2
2 L
1 2
60 [(5 1) 2 ] 1.92 mA
2 0.5

0 VGS VT VDS
 MOSFET On-Resistance

Ideal MOSFETs have infinite resistance when the

switch is open (off), and 0 resistance when it is
closed (on)
In practice, there is a non-zero resistance when the switch
is closed
V = I R R = VDS / ID

Example: the CMOS inverter with Vx = 5 V has Vf

close to 0 V, therefore VDS is close to 0 and the
NMOS transistor is in the triode region
W
RDS VDS / I D 1 /[ k n ' (VGS VT )] 1/2VDS2 term is neglected
L since VDS is quite small
 Example: MOSFET On-Resistance

Let kn' = 60A/V2, W/L = 2.0m/0.5m, VS = 0 V,

VG = 5 V, and VT = 1V
W
RDS VDS / I D 1 /[ k n ' (VGS VT )]
L
2
VDS / I D 1 /[60 (5 1)] 1k
0.5
 Characterizing Voltage Levels

The inverter is always used to determine the ranges

of high and low voltage levels

For NMOS transistors, when Vx = 0 V Vf = 5 V

When Vx = 5 V Vf depends on the resistance RDS

of the transistor (previously assumed to be 0) V
VDD DD
The closed NMOS switch acts as a resistor thereby
providing a voltage divider
R
Vf RDS Vf
V f VDD
Vx RDS R RDS
 Static Current in NMOS Transistors

If R = 25 k and RDS = 1 k, then

RDS 1
V f VDD 5 0.2V
RDS R 1 25

VDD
The static current flow (i.e. when Vx = VDD)
thru the NMOS inverter is
R
I stat V f / RDS 0.2V / 1k 0.2mA
Istat Vf

RDS
 CMOS Inverter Voltage Transfer
Vf

V OH = V DD Slope = 1

V OL = 0 V
VT V IL V IH V DD V T V DD
Vx
V DD
Maximum input voltage that will 2 Minimum input voltage that will
produce an output of logic 1 produce an output of logic 0
 Noise Margin

Electronic circuits are subjected to constant random

perturbations noise

Noise margin is the amount of voltage that can be

tolerated without affecting correct gate operation

NML = V IL Gnd
Slope = -1
NMH = VDD - VIH

VIL VIH VDD

 Parasitic Capacitance (1)

Transistors are fabricated with multiple layers of

materials
When different types of materials meet inside a transistor, a
capacitor may be created stores charge!!
Called parasitic (or stray) capacitance
This is an undesirable side effect

Ex: Inverter N2 creates a parasitic capacitance at A

 Parasitic Capacitance (2)

Parasitic capacitance slows the speed of the circuit

Voltages cannot change immediately must allow for the
capacitor to charge or discharge
C is charged to VDD when the PMOS transistor in N1 is closed
C is discharged to Gnd when the NMOS transistor in N1 is
closed
 Gate Delays

Parasitic capacitance results in gate delays

Propagation delay = time from Vx = VDD to VA = VDD
VDD

Vx
50% 50%

Gnd

Propagationdelay Propagationdelay

VDD
90% 90%
VA 50% 50%

Gnd 10% 10%

tr tf
rise time = time between fall time = time between VA
VA = .1 VDD to VA = .9 VDD = .9 VDD to VA = .1 VDD
 NMOS Power Dissipation

Power used must be small for VLSI circuits

For the NMOS inverter, when Vx = 0 V, no

current flows and no power is used

When Vx = VDD, steady state power PS = Istat

VDD

If there are
PS 10,000
I stat VDD inverters
0.2mA 5V on the chip,
1mW
then the power used is 10 W!
This is generally unacceptable
 Static vs Dynamic Power

Static power is dissipated by current flow in the

steady state when signals are not changing

Dynamic power is dissipated by current flow during

signal transitions

NMOS circuits consume static and dynamic power

CMOS circuits consume only dynamic power

 Dynamic Current Flow in CMOS (1)

Because of parasitic capacitance, current will flow in

CMOS during dynamic state changes

When Vx changes from 0 V to 5 V, the NMOS transistor

closes and the parasitic capacitance must be discharged
Current flows thru the NMOS transistor power must be
dissipated

ID

Vf

Vx
 Dynamic Current Flow in CMOS (2)

Similar situation when Vx changes from 5 V to 0 V,

the PMOS transistor closes and the parasitic
capacitance must be charged
Current flows thru the PMOS transistor power must be
dissipated

VDD

Vx ID

Vf
 CMOS Fan-In VDD

A CMOS NAND gate with fan-in = k would

have k times the propagation delay tp of Vf

a single inverter! V x1
1.7C
tp k
W
k n' VDD
L Vx
2

Propagation delay can be reduced

by producing transistors that have larger Vx
3

width W or smaller length L, but this

takes greater chip area

Vx
k
 CMOS Fan-Out

The capacitance at node f is proportional to the sum

of the capacitances contributed by each device
driven by the inverter
This larger capacitance results in longer propagation delays

V f for n =1
N1 VDD
f
x
V f for n = 4

Gnd
0 Time
 Transmission Gates

A gate that passes its value when a select control =

1, and gives high impedance when select = 0
s= 0

x f=Z

like a tri-state gate

s= 1
x f=x
s
PMOS used to pass logic 1 well s

x f
x f

s
s NMOS used to pass logic 0 well