0.2 Clocks in Digital ICs

Digital Integrated Circuits
Timing Issues
Digital Integrated Circuits2nd Timing Issues

1
Synchronous Timing
CLK
In Combinational
R1 R2
Cin Logic Cout Out

2
Timing
Definitions

3
Latch Parameters
D Q
Clk
T
Clk PWm
tsu
D
thold
tc-q td-q
Q
Delays can be different for rising and falling data transitions

4
Register Parameters
D Q
Clk
T
Clk
D thold
tsu
tc-q
Q
Delays can be different for rising and falling data transitions

5
Clock Uncertainties
4 Power Supply
3 Interconnect
2 6 Capacitive Load
Devices
7 Coupling to Adjacent Lines

5 Temperature
1 Clock Generation
Sources of clock uncertainty

6
Clock Nonidealities
Clock skew
Spatial variation in temporally equivalent clock edges;
deterministic + random, tSK
Clock jitter
Temporal variations in consecutive edges of the clock
signal; modulation + random noise
Cycle-to-cycle (short-term) tJS
Long term tJL
Variation of the pulse width
Important for level sensitive clocking

7
Clock Skew and Jitter
Clk
tSK
Clk tJS
Both skew and jitter affect the effective cycle time

Only skew affects the race margin

8
Clock Skew
# of registers
Earliest occurrence Latest occurrence

of Clk edge of Clk edge
Nominal /2 Nominal + /2
Insertion delay Clk delay

Max Clk skew

9
Positive and Negative Skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q
Logic Logic
CLK tCLK1 tCLK2 tCLK3
delay delay
(a) Positive skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q
Logic Logic
tCLK1 tCLK2 tCLK3
delay delay CLK

(b) Negative skew

10
Positive Skew
TCLK + d
TCLK
1 3
CLK1
d
CLK2 2 4
d + th
Launching edge arrives before the receiving edge

11
Negative Skew
TCLK + d
TCLK
1 3
CLK1
CLK2 2 4
d
Receiving edge arrives before the launching edge

12
Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic
CLK tCLK1 tCLK2
tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold
Minimum cycle time:

T - = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

13
Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic
CLK tCLK1 tCLK2
tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold
Hold time constraint:

t(c-q, cd) + t(logic, cd) > thold +
Worst case is when receiving edge arrives late
Race between data and clock

14
Impact of Jitter
TC LK
t j itter
CLK
-tji tte r
REGS Combinational
In Logic
CLK t log ic
tc-q , tc-q, cd t log ic, cd
ts u, thold
tjitter

15
Longest Logic Path in
Edge-Triggered Systems
TJI +
TSU
Clk
TClk-Q
TLM
T
Latest point Earliest arrival

of launching of next cycle

16
Clock Constraints in
Edge-Triggered Systems
If launching edge is late and receiving edge is early, the data will not be too late if:
Tc-q + TLM + TSU < T TJI,1 TJI,2 -
Minimum cycle time is determined by the maximum delays through the logic
Tc-q + TLM + TSU + + 2 TJI < T

Skew can be either positive or negative
17
Shortest Path
Earliest point
of launching
Clk
TClk-Q TLm
Clk
TH
Data must not arrive

Nominal
before this time
clock edge

18
Clock Constraints
in Edge-Triggered Systems
If launching edge is early and receiving edge is late:
Tc-q + TLM TJI,1 < TH + TJI,2 +

Minimum logic delay
Tc-q + TLM < TH + 2TJI+

19
How to counter Clock Skew?
Negative Skew
REG
REG
REG
. log Out
REG
In
Positive Skew

Clock Distribution
Data and Clock Routing

20
Flip-Flop Based Timing
Skew Flip-flop
Logic delay delay

TSU
Flip TClk-Q
-flop
=1
=0
Logic
Representation after
M. Horowitz, VLSI Circuits 1996.

21
Flip-Flops and Dynamic Logic
Logic delay
TSU
TSU TClk-Q
TClk-Q
=1
=1 =0
=0
Logic delay
Precharge Evaluate Precharge
Evaluate
Flip-flops are used only with static logic

22
Latch timing
tD-Q When data arrives
to transparent latch
Latch is a soft barrier
D Q
Clk
tClk-Q When data arrives

to closed latch
Data has to be re-launched

23
Single-Phase Clock with Latches

Latch
Logic
Tskl Tskl Tskt Tskt
Clk
PW
P

24
Latch-Based Design
L1 latch is L2 latch is transparent
transparent when = 1

when = 0
L1 L2
Logic
Latch Latch
Logic

25
Slack-borrowing
L1 L2 L1
In CLB_A CLB_B
D Q D Q D Q
a t p d,A b c t p d,B d e
CLK1 CLK2 CLK1

TC LK
CLK1
CLK2
slack passed to next stage

t pd,A tD Q tpd,B t DQ
a valid e valid
b valid c valid d valid

26
Latch-Based Timing
Skew
Static logic

L2 latch
L1
Logic
L2 =1
Latch Latch
L1 latch
Logic
Long =0
path
Can tolerate skew!

Short
path

27
Clock Distribution
H-tree
CLK
Clock is distributed in a tree-like fashion

28
More realistic H-tree
[Restle98]

29
The Grid System
GCL K
Driver
Driver
Driver
GCLK GCLK
No rc-matching
Large power
Driver
GCL K

30
Example: DEC Alpha 21164
Clock Frequency: 300 MHz - 9.3 Million Transistors
Total Clock Load: 3.75 nF
Power in Clock Distribution network : 20 W (out of 50)
Uses Two Level Clock Distribution:
Single 6-stage driver at center of chip

Secondary buffers drive left and right side
clock grid in Metal3 and Metal4
Total driver size: 58 cm!

31
21164 Clocking
tcycle= 3.3ns 2 phase single wire clock,
trise = 0.35ns tskew = 150ps distributed globally
2 distributed driver channels
Clock waveform
Reduced RC delay/skew
final drivers Improved thermal distribution
3.75nF clock load
58 cm final driver width
Local inverters for latching
Conditional clocks in caches to
reduce power
pre-driver More complex race checking
Device variation
Location of clock
driver on die
32
Clock Drivers

33
Clock Skew in Alpha Processor

34
EV6 (Alpha 21264) Clocking
600 MHz 0.35 micron CMOS
tcycle= 1.67ns
trise = 0.35ns tskew = 50ps

Global clock waveform
2 Phase, with multiple conditional
buffered clocks
2.8 nF clock load
40 cm final driver width
Local clocks can be gated off to save
power
Reduced load/skew
Reduced thermal issues
Multiple clocks complicate race
PLL
checking
35
21264 Clocking

36
EV6 Clock Results
ps ps
5 300
10 305
15 310
20 315
25 320
30 325
35 330
40 335
45 340
50 345
GCLK Skew GCLK Rise Times

(at Vdd/2 Crossings) (20% to 80% Extrapolated to 0% to 100%)

37
EV7 Clock Hierarchy
Active Skew Management and Multiple Clock Domains
+ widely dispersed
NCLK
(Mem Ctrl) drivers
+ DLLs compensate
DLL
DLL
DLL
static and low-
frequency variation
+ divides design and
verification effort
(L2 Cache)
(L2 Cache)
L2R_CLK
L2L_CLK
PLL
- DLL design and

GCLK verification is added
(CPU Core)
work
SYSCLK + tailored clocks
38
Self-timed and Asynchronous Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
1) Completion is ensured by careful timing analysis

2) Ordering of events is implicit in logic
Self-timed design
1) Completion ensured by completion signal

2) Ordering imposed by handshaking protocol

39
Synchronous Pipelined Datapath
R1 R2 R3 R4
In Logic Logic Logic
D Q Block #1 D Q Block #2 D Q Block #3 D Q
CLK tpd,reg tpd1 tpd2 tpd3

40
Self-Timed Pipelined Datapath
Req Req Req Req
Ack HS Ack HS Ack HS ACK
Start Done Start Done Start Done
R1 F1 R2 F2 R3 F3 Out
In
tpF1 tpF2 tpF3

41
Completion Signal Generation
LOGIC
In Out
NETWORK
Start DELAY MODULE Done
Using Delay Element (e.g. in memories)

42
Completion Signal Generation
Using Redundant Signal Encoding

43
Completion Signal in DCVSL
VDD VDD
Start B0
Done
B1
B0 B1
In1
In1
In2 PDN PDN
In2
Start

44
Self-Timed Adder
VDD VDD
Start Start
P0 P1 P2 P3 Done
C0 C1 C2 C3 C4 C4
C4 C4
C0 G0 G1 G2 G3 C3 C3
Start C2 C2
C1 C1
VDD
Start
Start
P0 P1 P2 P3
C0 C1 C2 C3 C4 C4 (b) Completion signal
C0 K0 K1 K2 K3
Start
(a) Differential carry generation

45
Completion Signal Using Current Sensing
VDD
Input Register
Start
Inputs Static CMOS Logic Output tdelay
A
GNDsense toverlap
Start
Current Sensor A B
tMDG
Done tpd-NOR
Done
Min Delay Generator B
Output valid

46
Hand-Shaking Protocol
Two Phase Handshake

47
Event Logic The Muller-C Element
A B Fn+1
A
0 0 0
C F 0 1 Fn
B 1 0 Fn
1 1 1
(a) Schematic (b) Truth table

VDD
VDD VDD
A B
A
S Q
F B
B F
R A F
B
(a) Logic
A B
B
(b) Majority Function
(c) Dynamic
48
2-Phase Handshake Protocol
Advantage : FAST - minimal # of signaling events (important for global

interconnect)
Disadvantage : edge - sensitive, has state

49
Example: Self-timed FIFO
In Out
R1 R2 R3
En Done
Reqi Req0
C C C
Acki Acko
All 1s or 0s -> pipeline empty

Alternating 1s and 0s -> pipeline full

50
2-Phase Protocol

51
Example
From [Horowitz]

52
Example

53
Example

54
Example

55
Also known as RTZ

Slower, but unambiguous

56
Implementation using Muller-C elements

57
Self-Resetting Logic
completion completion completion

detection detection detection
(L1) (L2) (L3)
Precharged Precharged Precharged
Logic Block Logic Block Logic Block
(L1) (L2) (L3)
VDD
Post-charge
int
out logic
A B C

58
Clock-Delayed Domino
GND
CLK1 CLK2 (to next stage)
VDD
Q1 (also D2)
D1 Pulldown
Network

59
Asynchronous-Synchronous Interface
fin
Synchronous system
Asynchronous
system
fCLK
Synchronization

60
Synchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events occurred
first
Synchronizer: Arbiter with clock as one of the
inputs
Problem: Circuit HAS to make a decision in limited
time - which decision is not important
Caveat: It is impossible to ensure correct operation
But, we can decrease the error probability at the
expense of delay

61
A Simple Synchronizer
CLK
I1
int
D Q
I2
CLK
Data sampled on rising edge of the clock
Latch will eventually resolve the signal value,

but ... this might take infinite time!
62
Synchronizer: Output Trajectories
2.0
Vout
1.0
0.0
0 100 200 300
time [ps]
Single-pole model for a flip-flop

63
Mean Time to Failure

64
Example
Tf = 10 nsec = T
Tsignal = 50 nsec
tr = 1 nsec
t = 310 psec
VIH - VIL = 1 V (VDD = 5 V)
N(T) = 3.9 10-9 errors/sec

MTF (T) = 2.6 10 8 sec = 8.3 years
MTF (0) = 2.5 sec

65
Influence of Noise
Uniform distribution
around VM
p(v)
logarithmic
reduction
T
0 VIL VIH
Still Uniform
Initial Distribution
Low amplitude noise does not influence synchronization behavior

66
Typical Synchronizers
2 phase clocking circuit 2
Q
1
Q 2
Using delay line

67
Cascaded Synchronizers Reduce MTF
In O1 O2 Out
Sync Sync Sync

68
Arbiters
Req1 Ack1
Req1 A
Arbiter
Req2 Ack2 Ack2
B
Ack1
Req2
(a) Schematic symbol
Req1 (b) Implementation

Req2
VT gap
A (c) Timing diagram
B
metastable
Ack1
t

69
PLL-Based Synchronization
Chip 1 Chip 2
Data
Digital Digital
System System
reference
fsystem = N x fcrystal clock
Divider PLL
PLL Clock
Buffer
fcrystal , 200<Mhz
Crystal
Oscillator

70
PLL Block Diagram
Reference Up
clock vcont
Phase Charge Loop
VCO
detector pump filter
Local Down
clock
Divide by
N
System
Clock

71
Phase Detector
Output before filtering
Transfer
characteristic

72
Phase-Frequency Detector
B A
Rst UP
D Q B
A UP = 0 UP = 0 UP = 1
A
DN = 1 DN = 0 DN = 0
Rst
D Q
DN
A B
B
(a) schematic (b) state transition diagram
A A
B B
UP UP
DN DN
(c) Timing waveforms

73
PFD Response to Frequency
UP
DN

74
PFD Phase Transfer Characteristic
Average (UP-DN)
VDD
-2 p
2p phase error (deg)

75
Charge Pump
VDD
UP To VCO Control Input
DN

76
PLL Simulation

77
Clock Generation using DLLs
Delay-Locked Loop (Delay Line Based)
fREF U
Phase Charge
D DL
Det Pump
Filter
fO
Phase-Locked Loop (VCO-Based)

fREF U
PD D CP VCO
N Filter
fO

78
Delay Locked Loop

79
DLL-Based Clock Distribution
Digital
VCDL
Circuit
CP/LF
Phase
Detector
Digital
GLOBAL CLK VCDL
Circuit
CP/LF
Phase
Detector

80

0.2 Clocks in Digital ICs

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Digital Integrated Circuits

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Delays can be different for rising and falling data transitions

Delays can be different for rising and falling data transitions

7 Coupling to Adjacent Lines

Sources of clock uncertainty

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Both skew and jitter affect the effective cycle time

Digital Integrated Circuits2nd Timing Issues

Earliest occurrence Latest occurrence

Insertion delay Clk delay

Digital Integrated Circuits2nd Timing Issues

CLK tCLK1 tCLK2 tCLK3

tCLK1 tCLK2 tCLK3

delay delay CLK

Digital Integrated Circuits2nd Timing Issues

Launching edge arrives before the receiving edge

Digital Integrated Circuits2nd Timing Issues

Receiving edge arrives before the launching edge

Digital Integrated Circuits2nd Timing Issues

CLK tCLK1 tCLK2

Minimum cycle time:

Digital Integrated Circuits2nd Timing Issues

CLK tCLK1 tCLK2

Hold time constraint:

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Latest point Earliest arrival

Digital Integrated Circuits2nd Timing Issues

Tc-q + TLM + TSU < T TJI,1 TJI,2 -

Tc-q + TLM + TSU + + 2 TJI < T

Data must not arrive

Digital Integrated Circuits2nd Timing Issues

Tc-q + TLM TJI,1 < TH + TJI,2 +

Tc-q + TLM < TH + 2TJI+

Digital Integrated Circuits2nd Timing Issues

Data and Clock Routing

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Flip-flops are used only with static logic

Digital Integrated Circuits2nd Timing Issues

tClk-Q When data arrives

Data has to be re-launched

Digital Integrated Circuits2nd Timing Issues

Tskl Tskl Tskt Tskt

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

CLK1 CLK2 CLK1

slack passed to next stage

Digital Integrated Circuits2nd Timing Issues

Can tolerate skew!

Digital Integrated Circuits2nd Timing Issues

Clock is distributed in a tree-like fashion

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Single 6-stage driver at center of chip

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

Digital Integrated Circuits2nd Timing Issues

trise = 0.35ns tskew = 50ps