Elec204 Lecture08

Combinational Circuit
Each output can be a function of n inputs, 2n

possible input combinations.
We can implement m different functions.
KU College of Engineering
Lecture 8 Elec 204: Digital Systems Design
1
Design Schemes
VLSI circuit: millions of gates

Not manageable
Need to divide sub-circuits
Divide-and-Conquer Approach
Hierarchical Design
Broke circuits into pieces of blocks
Each block has a certain I/O
2
Design
example:
Hierarchical
and
Reusable
3
Hierarchical Block Diagram
4
Top-Down versus Bottom-Up
A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
Designs usually proceed from both directions
simultaneously
Top-down design answers: What are we building?
Bottom-up design answers: How do we build it?
Top-down controls complexity while bottom-up focuses on
the details
5
Bottom-Up
Design
6
Integrated Circuits
Integrated circuit (informally, a chip) is a
semiconductor crystal (most often silicon) containing
the electronic components for the digital gates and
storage elements which are interconnected on the chip.
Terminology - Levels of chip integration
SSI (small-scale integrated) - fewer than 10 gates
MSI (medium-scale integrated) - 10 to 100 gates
LSI (large-scale integrated) - 100 to thousands of gates
VLSI (very large-scale integrated) - thousands to 100s of
millions of gates
7
Technology Parameters
Specific gate implementation technologies are characterized
by the following parameters:
Fan-in the number of inputs available on a gate
Fan-out the number of standard loads driven by a gate output
Logic Levels the signal value ranges for 1 and 0 on the inputs and 1
and 0 on the outputs
Noise Margin the maximum external noise voltage superimposed on
a normal input value that will not cause an undesirable change in the
circuit output
Cost for a gate - a measure of the contribution by the gate to the cost
of the integrated circuit
Propagation Delay The time required for a change in the value of a
signal to propagate from an input to an output
Power Dissipation the amount of power drawn from the power
supply and consumed by the gate
8
Propagation Delay
Propagation delay is the time for a change on an input of a
gate to propagate to the output.
Delay is usually measured at the 50% point with respect to
the H and L output voltage levels.
High-to-low (tPHL) and low-to-high (tPLH) output signal
changes may have different propagation delays.
High-to-low (HL) and low-to-high (LH) transitions are
defined with respect to the output, not the input.
An HL input transition causes:
an LH output transition if the gate inverts and
an HL output transition if the gate does not invert.
9
Propagation Delay (continued)
Propagation delays measured at the midpoint between the

L and H values
What is the expression for the tPHL delay for:
a string of n identical buffers?
a string of n identical inverters?
10
Propagation Delay Example
IN (volts)
OUT (volts) Find tPHL, tPLH and tpd for the signals given
t (ns)
1.0 ns per division
11
Delay Models
Transport delay - a change in the output in
response to a change on the inputs occurs after a
fixed specified delay
Inertial delay - similar to transport delay, except
that if the input changes such that the output is to
change twice in a time interval less than the
rejection time, the output changes do not occur.
Models typical electronic circuit behavior, namely,
rejects narrow pulses on the outputs
12
Delay Model Example
A
B
A B:
No Delay
(ND) a b c d e
Transport
Delay (TD)
Inertial
Delay (ID)
0 2 4 6 8 10 12 14 16 Time (ns)
Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns
13
Fan-out
Fan-out can be defined in terms of a
standard load
Example: 1 standard load equals the load
contributed by the input of 1 inverter.
Transition time -the time required for the gate
output to change from H to L, tHL, or from L to
H, tLH
The maximum fan-out that can be driven by a
gate is the number of standard loads the gate
can drive without exceeding its specified
maximum transition time
14
Fan-out and Delay
The fan-out loading of a gates output
affects the gates propagation delay
Example:
One realistic equation for tpd for a NAND gate
with 4 inputs is:
tpd = 0.07 + 0.021 SL ns
SL is the number of standard loads the gate is
driving, i. e., its fan-out in standard loads
For SL = 4.5, tpd = 0.165 ns
15
Cost
In an integrated circuit:
The cost of a gate is proportional to the chip area
occupied by the gate
The gate area is roughly proportional to the number and
size of the transistors and the amount of wiring
connecting them
Ignoring the wiring area, the gate area is roughly
proportional to the gate input count
So gate input count is a rough measure of gate cost
If the actual chip layout area occupied by the gate
is known, it is a far more accurate measure
16
Design Procedure
1. Specification
Write a specification for the circuit if one is not already available
2. Formulation
Derive a truth table or initial Boolean equations that define the
required relationships between the inputs and outputs, if not in the
specification
3. Optimization
Apply 2-level and multiple-level optimization
Draw a logic diagram or provide a netlist for the resulting circuit
using ANDs, ORs, and inverters
4. Technology Mapping
Map the logic diagram or netlist to the implementation technology
selected
5. Verification
Verify the correctness of the final design
17
Design Example
1. Specification
BCD to Excess-3 code converter
Transforms BCD code for the decimal digits to Excess-3
code for the decimal digits
BCD code words for digits 0 through 9: 4-bit patterns 0000
to 1001, respectively
Excess-3 code words for digits 0 through 9: 4-bit patterns
consisting of 3 (binary 0011) added to each BCD code
word
Implementation:
multiple-level circuit
NAND gates (including inverters)
18
Design Example (continued)
2. Formulation
Conversion of 4-bit codes can be most easily formulated by a
truth table
Input BCD Output Excess-3
Variables
- BCD: ABCD WXYZ
A,B,C,D 0000 0011
0001 0100
Variables
0010 0101
- Excess-3
0011 0110
W,X,Y,Z
0100 0111
Dont Cares 0101 1000
- BCD 1010 0110 1001
to 1111 0111 1010
1000 1011
1001 1011
19
3. Optimization
a. 2-level using
K-maps
W = A + BC + BD
X = BC + BD +
BCD
Y = CD + CD
Z = D
20
3. Optimization (continued)
b. Multiple-level using transformations
W = A + BC + BD
X = BC + BD + BCD
Y = CD + CD
Z = D G = 7 + 10 + 6 + 0 = 23
Perform extraction, finding factor:
T1 = C + D
W = A + BT1
X = BT1 + BCD
Y = CD + CD
Z = D G = 2 + 1 + 4 + 7 + 6 + 0 = 19
21
3. Optimization (continued)
b. Multiple-level using transformations
T1 = C + D
W = A + BT1
X = BT1 + BCD
Y = CD + CD
Z = D G = 19
An additional extraction not shown in the text since it uses a Boolean
transformation: ( CD= (C + D) = T1 ):
W = A + BT1
X = BT1 + BT1
Y = CD + T1
Z = D G = 2 +1 + 4 + 6 + 4 + 0 = 16!
22
4. Technology Mapping
Mapping with a library containing inverters and 2-input NAND,
2-input NOR, and 2-2 AOI gates
A A
W W
B X B
X
C
C Y D Y
D
Z
Z
23
Technology Mapping
Chip design styles

Cells and cell libraries
Mapping Techniques
NAND gates
NOR gates
Multiple gate types
Programmable logic devices
24
Chip Design Styles
Full custom - the entire design of the chip down to the smallest detail
of the layout is performed
Expensive
Justifiable only for dense, fast chips with high sales volume
Standard cell - blocks have been design ahead of time or as part of
previous designs
Intermediate cost
Less density and speed compared to full custom
Gate array - regular patterns of gate transistors that can be used in
many designs built into chip - only the interconnections between gates
are specific to a design
Lowest cost
Less density compared to full custom and standard cell
25
Cell Libraries
Cell - a pre-designed primitive block

Cell library - a collection of cells available for design
using a particular implementation technology
Cell characterization - a detailed specification of a cell for
use by a designer - often based on actual cell design and
fabrication and measured values
Cells are used for gate array, standard cell, and in some
cases, full custom chip design
26
Example Cell Library
Typical
Typical Input-to- Basic
Cell Cell Normalized Input Output Function
Name Schematic Area Load Delay Templates
0.04
Inverter 1.00 1.00
1 0.012 3 SL
0.05
2NAND 1.25 1.00
1 0.014 3 SL
0.06
2NOR 1.25 1.00
1 0.018 3 SL
0.07
2-2 AOI 2.25 0.95
1 0.019 3 SL
27
Verification
Verification - show that the final circuit designed
implements the original specification
Simple specifications are:
truth tables
Boolean equations
HDL code
If the above result from formulation are not the
original specification, it is critical that the
formulation process be flawless for the
verification to be valid!
28
Basic Verification Methods
Manual Logic Analysis
Find the truth table or Boolean equations for the final circuit
Compare the final circuit truth table with the specified truth table,
or
Show that the Boolean equations for the final circuit are equal to
the specified Boolean equations
Simulation
Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL description
using test input values that fully validate correctness.
The obvious test for a combinational circuit is application of all
possible care input combinations from the specification
29
Programmable Implementation Technologies
Why programmable logic?

Programmable logic technologies
Read-Only Memory (ROM)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
30
Why Programmable Logic?
Facts:
It is most economical to produce an IC in large volumes
Many designs required only small volumes of ICs
Need an IC that can be:
Produced in large volumes
Handle many designs required in small volumes
A programmable logic part can be:
made in large volumes
programmed to implement large numbers of different low-volume
designs
31
Programmable Logic - Additional Advantages
Many programmable logic devices are field- programmable,
i.e., can be programmed outside of the manufacturing
environment
Most programmable logic devices are erasable and
reprogrammable.
Allows updating a device or correction of errors
Allows reuse the device for a different design - the ultimate in re-
usability!
Ideal for course laboratories
Programmable logic devices can be used to prototype design
that will be implemented for sale in regular ICs.
Complete Intel Pentium designs were actually prototype with
specialized systems based on large numbers of VLSI programmable
devices!
32
Programming Technologies
Programming technologies are used to:

Control connections
Build lookup tables
Control transistor switching
The technologies
Control connections
Mask programming
Fuse
Antifuse
Single-bit storage element
33
Programming Technologies
The technologies (continued)

Build lookup tables
Storage elements (as in a memory)
Transistor Switching Control
Stored charge on a floating transistor gate
Erasable
Electrically erasable
Flash (as in Flash Memory)
Storage elements (as in a memory)
34
Technology Characteristics
Permanent - Cannot be erased and reprogrammed
Mask programming
Fuse
Antifuse
Reprogrammable
Volatile - Programming lost if chip power lost
Single-bit storage element
Non-Volatile
Erasable
Electrically erasable
Flash (as in Flash Memory)
35
Programmable Configurations
Read Only Memory (ROM)

a fixed array of AND gates and a programmable array of OR gates
a programmable array of AND gates feeding a fixed array of OR
gates.
a programmable array of AND gates feeding a programmable array
of OR gates.
Complex Programmable Logic Device (CPLD) /Field-
Programmable Gate Array (FPGA)
complex enough to be called architectures
36
ROM, PAL and PLA Configurations
Fixed Programmable
Inputs Programmable Outputs
AND array
Connections OR array
(decoder)
(a) Programmable read-only memory (PROM)
Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array
(b) Programmable array logic (PAL) device
Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array
(c) Programmable logic array (PLA) device

37
Read Only Memory
Read Only Memories (ROM) or Programmable Read Only Memories (PROM)
have:
N input lines,
M output lines, and
2N decoded minterms.
Fixed AND array with 2N outputs implementing all N-literal minterms.
Programmable OR Array with M outputs lines to form up to M sum of minterm
expressions.
A program for a ROM or PROM is simply a multiple-output truth table
If a 1 entry, a connection is made to the corresponding minterm for the corresponding
output
If a 0, no connection is made
Can be viewed as a memory with the inputs as addresses of data (output values),
hence ROM or PROM names!
38
Read Only Memory Example
Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
The fixed "AND" array is a D7 X X X
decoder with 3 inputs and 8 D6
outputs implementing minterms. D5 X X
D4 X
The programmable "OR
A A2 D3 X
array uses a single line to D2
B A1 D1 X X
represent all inputs to an X
C A0 D0
OR gate. An X in the
array corresponds to attaching the
minterm to the OR
Read Example: For input (A2,A1,A0)
= 011, output is (F3,F2,F1,F0 ) = 0011. F3 F2 F1 F0
What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?
39
The PAL is the opposite of the ROM, having a programmable set
of ANDs combined with fixed ORs.
Disadvantage
ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
Advantages
For given internal complexity, a PAL can have larger N and M
Some PALs have outputs that can be complemented, adding POS
functions
No multilevel circuit implementations in ROM (without external
connections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.
40
AND gates inputs
Programmable Array Logic 0 1 2 3 4 5 6 7 8 9
X
Product 1
Example term
2
X X
F1
3
4-input, 3-output PAL with
I 1= A
fixed, 3-input OR terms X X X
4
What are the equations for F1 X X
5 F2
through F4?
X X
F1 = C + AB 6
I2 = B
F2 = ABC + AC + AB X X
7
F3 = AD + BD + F1
X X
F4 = AB + CD + F1 8 F3
X
9
I3 = C
X X
10
X X
11 F4
X
12
I4 = D
0 1 2 3 4 5 6 7 8 9
41
Compared to a ROM and a PAL, a PLA is the most flexible having a
programmable set of ANDs combined with a programmable set of
ORs.
Advantages
A PLA can have large N and M permitting implementation of equations
that are impractical for a ROM (because of the number of inputs, N,
required
A PLA has all of its product terms connectable to all outputs, overcoming
the problem of the limited inputs to the PAL ORs
Some PLAs have outputs that can be complemented, adding POS
functions
Disadvantage
Often, the product term count limits the application of a PLA. Two-level
multiple-output optimization reduces the number of product terms in an
implementation, helping to fit it into a PLA.
42
Programmable Logic Array Example
A
What are the equations for F1 and F2?
B Could the PLA implement the
functions without the XOR gates?
C
X X 1 X X AB
X X 2 X BC X Fuse intact
Fuse blown
X X 3 X AC
X X 4 X AB
X 0
C C B B AA
X 1
F1
3-input, 3-output PLA with 4
product terms F2
43

Elec204 Lecture08

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Combinational Circuit

Each output can be a function of n inputs, 2n

VLSI circuit: millions of gates

Propagation delays measured at the midpoint between the

Chip design styles

Cell - a pre-designed primitive block

Why programmable logic?

Programming technologies are used to:

The technologies (continued)

Read Only Memory (ROM)

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

(c) Programmable logic array (PLA) device

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