DESIGN AND

IMPLEMENTATION OF UART
USING
FPGA BOARD
Under the Guidance of Ch.Sumanth - 13071A04D4
G.Shanthi I.N.S Manoj - 13071A04E4
Assistant Prof. D.Nithish -13071A04G2
Dept. of ECE E.Shiva Prasad - 14075A0433
 Universal Asynchronous Receiver Transmitter
(UART)

Universal Asynchronous Receiver Transmitter(UART) is a

kind of serial communication protocol; mostly used for
short-distance, low speed, low-cost data exchange between
computer and peripherals.

UARTs are used for asynchronous serial data communication

by converting data from parallel to serial at transmitter with
some extra overhead bits using shift register and vice versa at
receiver
Different devices with UART
BLOCK DIAGRAM OF UART
 Field Programmable Gate Array
(FPGA)
FPGA or Field Programmable Gate
Arrays can be programmed or
configured by the user or designer
after manufacturing and during
implementation

The programming of the FPGA is

done using a logic circuit diagram or a
source code using a Hardware
description Language (HDL) to
specify how the chip should work.
 Advantages of FPGA board

1. Ability to re-program in the field to fix bug.

2. High-Speed.
3. Low cost.
Circuit diagram
 Simulation software - Modelsim
Modelsim is a multi-language
HDL simulation environment by
for simulation of
hardware description languages
such as VHDL, Verilog and
SystemC, and includes a built-in
C debugger. Modelsim can be
used independently, or in
conjunction with Altera Quartus
or Xilinx ISE.
Data framing in UART
 BIST Architecture in UART
BIST means Built In Self Test through which we can estimate
whether the data that is transmitted through UART
communication is correct or not.
 Transmit Module
The function of transmit module is to convert the sending 8-
bit parallel data into serial data, adds start bit at the head of
the data as well as stop bits at the end of the data.
This state machine has 4 states:
1. Idle (free),
2. Start (transmits start bit),
3. Data (Framing of Data),
4. End (Transmits stop bit).
 Receiver Module
During the UART reception, the serial data and the
receiving clock are asynchronous, so it is very important to
correctly determine the start bit of a frame data. The
receiver module receives data from RXD pin. The state
machine includes four states:

1. Idle (waiting for the start bit),

2. Shift (waiting for last bit),
3. Parity(checks for parity bit),
4. Stop(receiving stop bit) .