Acknowledgement: This presentation is adapted from
Professor Janak Patels tutorial on the same topic available on the web at: http://courses.ece.uiuc.edu/ece543/docs/DelayFault_6_per_page.pdf Outline Common Fault Models (Review) Defects and Delay Faults Delay Fault Models Transition Faults Path Delay Faults Robust Path Test Non-robust Path Test
Delay Fault Testing Tutorial 2
Common Fault Models Fault Model Definition Stuck-at Fault (SAF) Logic line stuck at 0 or 1 (can be single or multiple) Bridging Signals x and y become AND(x,y) or OR(x,y) Stuck-open Signal x stuck in some previous state Delay An I/O path between clocked elements has excessive delay Coupling Signals x and y become F(x,y) Pattern Interference Signals interact in space & time
Delay Fault Testing Tutorial 17 Delay Fault Testing Tutorial 18 Delay Fault Testing Tutorial 19 Delay Fault Testing Tutorial 20 Delay Fault Testing Tutorial 21 Delay Fault Testing Tutorial 22 Exercise Consider the 4-Nand implementation of the XOR gate in the previous slide. There are six I/O paths hence 12 path delay faults. For each of these faults, determine if it is robustly testable, only non-robustly testable or not testable (functionally redundant). Provide justification for your answers.
Delay Fault Testing Tutorial 23
Delay Fault Testing Tutorial 24 Delay Fault Testing Tutorial 25 Broadside is also called launch-off-capture test. Skewed-Load is also called launch-off-shift test. Delay Fault Testing Tutorial 26 Delay Fault Testing Tutorial 27 Delay Fault Testing Tutorial 28 Timing for launch-off-capture Transition-delay fault testing
This figure is borrowed from the paper, Ahmed et al., ITC-2005, Paper 11.1 Delay Fault Testing Tutorial 32 Delay Fault Testing Tutorial 33 (See Prof. Patels website for details on Segment Test) Delay Fault Testing Tutorial 34 Delay Fault Testing Tutorial 35 Delay Fault Testing Tutorial 36