AXI,AHB PROTOCOLS

Error response(ERR)
An error response is given by the slave acknowledging
the master about Txn status.
A slave informs the master if there is a error condition
associated with a transfer.
AXI,AHB allows responses for both read and write
transactions.
Error response in AXI is given by RRESP[1:0],
BRESP[1:0] and in AHB HRESP
TRANSFERS in AHB
Basic transfers
Transfers are 4 types based on HTRANS[1:0]
Burst transfers
Waited transfers HTRANS[1:0] Transfer type

b 00 IDLE
b 01 BUSY
b 10 NONSEQ
Locked transfers uses HMASTLOCK
b 11 SEQ
Error response in AHB
AHB error response consists of HRESP and HREADY
AHB response is given as OKAY or ERROR.
Three ways to complete a transfer
Cont..
OKAY indicates
Transfer Successful
Slave requires additional cycles to complete request

ERROR indicates
ERROR occurred during the transfer
In AHB
Transfers in AHB completes in 3 ways
Transfer done
Transfer pending
Inserts wait state to complete transfer not more than
16 waits.
Error response
Requires 2 cycles
If more cycles req, wait states are inserted by slave
In AHB, Error response
Error response in AXI
AHB error response consists of HRESP and HREADY
Read response comes along
with read data from slave
Write response comes in
write response channel
RESPONSE TYPES IN AXI
Normal Access
Exclusive access
Slave Error (SLVERR)
Decode Error (DECERR)
NORMAL ACCESS
Response OKAY indicates the following
Success of normal access
Failure of Ex-access
an Ex-access given to a slave that doesn't support it
Exclusive Access
Response EXOKAY says
Success of EX-access
SLVERR
Indicates unsuccessful Txn like
FIFO/Buffer full/empty conditions.
Unsupported size.
Writing to read-only.
Timeout condition in slave
Accessing an address where there is no register
Accessing an disabled or power-down Fn
DECERR
When master gives a address where there is no slave
interconnect give error.
Interconnect cant decode a slave, it sends to default
slave to give the response.
Protocol acquires that all the defined no. of Txns to be
completed.
Exclusive access Description
Implements semaphore opn without requiring the bus
to be locked during the Txn.
Doesnt effect critical bus latency or max BW.
RRESP,BRESP indicates the success or failure.
ARLOCK[1:0],AWLOCK[1:0] provides the following
access
00-Normal access
01-Exclusive access
10-Locked access
11-reserved
Ex-access process
Master performs Ex-read on an address
After sometime Master tries to complete the Opn by
performing Ex-write to same address
Response is given as
SUCCESS if no other master writes to the same address
b/w read & write access
FAIL if other master writes
 Perspective of Master
Perspective of Slave
Restrictions
Size, length of Ex-write and Preceding Ex-read should
be with same ID.
Addr of Ex-access should be aligned with total no of
bytes in Txn.
Addr od EX-Read, Ex-Write should be same.
ARID,AWID and control signal must be same.
1,2,4,8,16,32,64,128 bytes can be transferred.
LOCKED ACCESS
In locked transfer interconnect must ensure that only
particular master is allowed to access slave
Until the unlocked transfer from the same master is
completed
Arbiter takes care of it.
Master must ensures no other outstanding txns
waiting to complete.
Before unlocking master must ensure the completion
of txns.
Cache support
Bufferable (B)
Cacheable(C)
Read allocate(RA)
Write allocate(WA)
Protection Unit support
Normal or privileged
Secure or non-secure
Instruction or Data
Any queries