Introduction to Computer Engineering

Lecture 9: Combinational Logic, Mixed Logic

 Logic circuits
N Combinational M
 Combinational inputs outputs
circuits

 Sequential outputs
inputs
Combinational
circuits

Storage
Element

delay
 N Combinational M
inputs circuits outputs

 Outputs, “at any time”, are determined by the input combination

 When input changed, output changed immediately
 Note that real circuits are imperfect and have “propagation delay”
 A combinational circuit
 Performs logic operations that can be specified by a set of Boolean
expressions
 Can be built hierarchically

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 X0
9-input Odd Function
X1
X2
X3
9-input Z
X4
X5
Odd X0 A0 3-input
X1 A1 B0
X6 Function X2 A2 Odd
X7 Function
X8
X3 A0 3-input A0 3-input
X4
X5
A1
A2 Odd B0 A1
A2 Odd Z
Function Specification: Function Function
To detect odd number X6 A0 3-input
of “1” inputs, i.e. X7
X8
A1
A2 Odd B0
Z=1 when there is an Function
odd number of “1”
present in the inputs

How to design a 3-input Odd Function?

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A B C F
BC
0 0 0 0 A 00 01 11 10

0 0 1 0 1
0 0 1 1
1 1 0 1 0
0 1 0 1

0 1 1 0

1 0 0 1 F  A BC  ABC  A BC  ABC
1 0 1 0  A(BC  BC)  A(BC  BC)
1 1 0 0
 A(B  C)  A(B  C)
1 1 1 1
 A  (B  C)
 A BC
 X0
9-input Odd Function
X1
X2
X3
9-input Z
X4
X5
Odd X0 A0 3-input
X1 A1 B0
X6 Function X2 A2 Odd
X7 Function
X8
X3 A0 3-input A0 3-input
X4
X5
A1
A2 Odd B0 A1
A2 Odd Z
Function Function
X6 A0 3-input
X7 A1 B0
X8 A2 Odd
3-input Odd function: Function
B0=A0A1A2

A0
B0
A1
A2
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 F(A, B, C, D)  BC  A D

B
C
F

A
D

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 Enable component reuse

 Allow a digital logic circuit designer to

implement a combinational logic with
 Only NAND gates
 Only NOR gates
 Only NAND and NOR gates

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9
 Implement all ORs in the Boolean function
 Implement all ANDs in the Boolean function
 Forget all the inversion at this moment

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 F(A, B, C, D)  BC  A D

B
C

A
D

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 Draw “Vertical Bars” in the circuits where all
complements in the Boolean equation occur

 Draw a bubble on each Vertical Bar

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 F(A, B, C, D)  BC  A D

B
C

A
D

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 Convert each gate to the desired gate
 If only NAND gate is available, insert a bubble in
front of the AND gate
 If only OR gate is available, insert a bubble in front
of the OR gate

 Using DeMorgan’s Law in the process

 OR  NAND: by adding 2 bubbles on the inputs
side of OR
 AND  NOR: by adding 2 bubbles on the inputs
side of the AND
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 F(A, B, C, D)  BC  A D
Assume this design uses NAND gates only

B
C

A
D

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 Balance the bubbles on each wire, i.e. even
out the number of bubbles on every wire
 If there is odd number of bubbles on a wire,
add an inverter (i.e. a bubble)
 And remove those “vertical bars with
bubbles” which are used to help only, not in
the circuits

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 F(A, B, C, D)  BC  A D
Assume this design uses NAND gates only

B
C

A
D

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 Inverters can be implemented by either a NAND or a
NOR gate
 Wiring the inputs together

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 F(A, B, C, D)  BC  A D

Assume this design uses NAND gates only

B
C

A
D
 F(A, B, C, D)  BC  A D

Assume this design uses NAND gates only

B
C

A
D

6 NAND gates are used

 How about build the prior circuits with only
NOR gates?

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 F(A, B, C, D)  BC  A D

B
C

A
D
 F(A, B, C, D)  BC  A D

B
C

A
D

Add vertical bar for

each inversion
 F(A, B, C, D)  BC  A D
Assume this design uses NOR gates only

B
C

A
D
=

Convert each gate

to a NOR

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 F(A, B, C, D)  BC  A D
Assume this design uses NOR gates only

B
C

A
D

Balance number of
Bubbles on each wire

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 F(A, B, C, D)  BC  A D
Assume this design uses NOR gates only

B
C

A
D
Balance number of
bubbles on each wire
and substitute all gates
to NOR

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 F(A, B, C, D)  BC  A D
Assume this design uses NOR gates only

B
C

7 NOR gates are used

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 F  A  B  C  A (B  C  D))
C
D
B
A

Implement the logic circuits by ignoring all inversions

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 F  A  B  C  A (B  C  D))
C
D
B
A

Add vertical bar/bubble for each inversion

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 F  A  B  C  A (B  C  D))
C
D
B
A

Assume this design uses NAND gates only

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 F  A  B  C  A (B  C  D))
C
D
B
A

Balance the bubbles for each wire w/ inverters

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 F  A  B  C  A (B  C  D))
C
D
B
A

Remove the vertical bars/bubbles

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 F  A  B  C  A (B  C  D))
C
D
B
A

Replace all the gates to NAND gates

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 F  A  B  C  A (B  C  D))
C
D
B
A

Final mixed logic uses 11 NAND gates

(one of them is a triple-input NAND gate)

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B F  A CA BD
D

Implement the logic circuits by ignoring all inversions

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B F  A CA BD
D

Add vertical bar/bubble for each inversion

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B
F  A CA BD
D

Assume this design uses NOR gates only

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B
F  A CA BD
D

Balance the bubbles for each wire w/ inverters

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B F  A CA BD
D

Remove the vertical bars/bubbles

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B
F  A CA BD
D

Replace all the gates to NOR gates

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B F  A CA BD
D

Final mixed logic uses 9 NOR gates

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