Using emulation for

RTL performance verification

June 4, 2014

DaeSeo Cha
Infrastructure Design Center
System LSI Division
Samsung Electronics Co., Ltd.

1
 Current Performance Verification
Architectural Performance Exploration
System Requirement SystemC model, real workload aware performance
analysis

System Architecture Architectural Performance Verification

Specification System C model Inaccuracy

RTL Performance Verification

RTL Integration Subsystems/full chip using logic simulation Slow

RTL Performance Verification

FPGA
Sub-system only Capacity

RTL Performance Verification

Post-Silicon Full chip Too late in development stage

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 New Approach for Performance Verification
System Requirement
UVM Testebench

System Architecture Big capacity

Specification Accurate Full chip
Cycle Accuracy
Fast
100X+
RTL Integration
log log log log
Fast Analysis Early Stage
Correlation/Compare RTL freeze
FPGA GUI Analysis Environment
(PRISM)
* PRISM: Samsung In-house Tool

Post-Silicon Summary

Fast and Accurate Performance Verification

3 3/13
 Performance Verification Platform
Environment
Reuse existing UVM simulation environment without any modification
Add PV(Performance Verification) components

PV components
Monitor: Collect various performance metrics
Traffic Generator: Random or replay RTL IPs traffic
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 UVM Co-emulation Environment
UVM Architecture for Co-emulation
sw_top UVM testbench
prim_top Simulator
tb_top
Incr_top Bus
AXIUVC
bus Module
Test scenario
hw_top DUT
Register Model
Interface Emulator
Interface
Virtual sequencer
Sequence
REG2BUS adapter
DUT
Register predictor

Interrupt

Simulation environment
- Incremental elaboration having primary, incremental snapshot
- Building test scenarios by combining testbench and design in full-chip
Emulation environment
- DUT runs in emulator, incremental elaboration scheme used in emulator
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 Performance Monitor -1/2
Performance Metrics
Latency: Min/Max/Average, time-varying, accumulated, distributed
Bandwidth: Min/Max/Average, time-varying, accumulated, distributed
Utilization: Min/Max/Average, time-varying, accumulated, distributed
Address pattern
Response time PM

Customized metrics like IPs internal signals (FIFO level)

Implementation
Synthesizable code for both simulation and emulation
Log file
Collect performance metrics on AXI interface
Issue PRISM
PM: performance monitor
Run-time overhead in emulation
Synchronization overhead between emulator and simulator

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 Performance Monitor 2/2
Experiments
PV results should be recorded in-order
Many experiments are done to reduce run-time overhead
Method Description tbcall sync Overhead
No PV Monitor Baseline 398 -
$display Sync with TB using $fdisplay() 32,798 81X
GFIFO Buffering monitored transaction 472 1.12X
Collecting process in back ground

GFIFO
Transactions are collected in order, it is congruent with the SW simulation
Parallel execution of monitor transaction in SW Improve performance
bit a; bit [5:0] b; int c;
bit a; bit [5:0] b; int c; function void my_mon(bit x1, bit [5:0] x2, int x3);
always @(clk) begin $fdisplay(%d %d %d, x1, x2, x3);
$fdisplay ( %d %d %d, a, b, c); endfunction;
end Simulation Monitor initial $ixc_ctrl("gfifo", my_mon");
always @(clk) begin my_mon(a, b, c) end GFIFO
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 Performance Analysis Environment
PRISM (Performance Visualization System)
Charting PV results in GUI
Easy to find a performance issue by viewing PV results in a single GUI

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 Experimental Result
Application
Multimedia test scenarios such as video playback, camera recording

Run-time speed
+100x faster than simulation
Bugs found
Critical bugs and design weak points which would not been detected
during simulation-based verification

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 Conclusion
PV using emulator is a mainstream solution
Very fast bring up using UVM Co-emulation
Reusing UVM full-chip testbench without any modification
PV in early design development stage with cycle accuracy
+100x faster speed compared with simulation approach
Efficient PV analysis by PRISM

Future Work
Add more features to PRISM - correlation, smart PV report etc.
Develop ACE PV Monitor for dealing with cache-coherency
Deploy UVM Co-emulation for other test scenarios

10 10/13
 Thank you

11 11/13