Documente Academic
Documente Profesional
Documente Cultură
Shmuel Wimer
Bar Ilan University, School of Engineering
August 2010 1
A memory has 2n words of 2m bits each. Usually 2n >> 2m,
(e.g. 1M Vs. 64) which will result a very tall structure.
Bit-line Conditioning
Word-lines
Row Decoder Bit-lines
Array of 2nx2m
cells, organized
in 2n-k rows by
2m+k columns
n-k
k
Column
n
Circuitry
Column
Decoder 2m bits
The value of bit-line needs to override the value stored at the cell. It
requires careful design of transistor size for proper operation.
August 2010 4
12-Transistor SRAM Cell
bit
write When read=1 the output of
the lower tri-state inverter
write gets connected to the bit so
cells value appears on the
read bit-line.
August 2010 5
Though robust, 12-transistor cell consumes large area.
Since it dominates the SRAM area, a 6-transistor is
proposed, where some of the expense is charged on
the peripheral circuits.
word
6-Transistor
SRAM Cell
bit bit
August 2010 6
Layout of IBM 0.18u SRAM cell
Lithography simulation
Layout design
Silicon
August 2010 7
Read Write Operations
SRAM operation is divided into two phases called 1 and 2, which
can be obtained by clk and its complement.
Pre-charge both bit-lines high.
A A
Since bit-line was high, the 0
N2 N4 node will go positive for a
short time, but must not go too
N1 N3
high to avoid cell switch.
August 2010 8
A bit
Read
Stability
word
P1 P2 Weak
A A Medium
N2 N4
Strong
N1 N3
bit bit
August 2010 10
A
bit
Writability
August 2010 11
SRAM Column Read Operation
1
Bit-line Conditioning
2
2
word
word
bit
It is possible to break
the AND gates into few
levels as shown in the word15
4:16 decoder.
August 2010 14
A3 A2 A1 A0 word15 word1 word0
Pre-coded Lines
Vcc
2x x 1 1
word0
x 1 1
word1
2x x 1 1
word2
x 1 1
word3
August 2010 16
Sum-addressed Decoders
August 2010 17
Sum-addressed Decoders
If we know A and B, we can deduce what must be the
carry in of every bit if it would happen that K = A + B .
Ai Bi Ki Cin_i Cout_i
(required) (generated)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1
August 2010 19
Theorem: If for every 1 i n Cin_(i 1) Cout_i ,
then A B K .
(2) Cout_i Ai Bi Ki Ai Bi .
We'll show that for every 1 i n,
zi Cin _i
Cout_(i 1) implies ei A B i K i ,
which will prove the theorem.
August 2010 20
zi Cin_i
Cout_(i 1) implies
ei A B i Ki implies
(4) ei 1 A B Cin K 1.
i i _i i
Assume that zi 1.
(5) Ai Bi Ki Ai 1 Bi 1 Ki 1 Ai 1Bi 1 1.
August 2010 21
By induction the theorem holds for i 1, hence
(6) Ki 1 A B i 1 ,
which is Ki 1 Ai 1 Bi 1 Cin_(i 1) .
Substitution of (6) in the second brakets of (5) and
further manuipulations turns the braket into
Ai Bi Ki Cin_i 1, implying ei 1.
August 2010 22
Cout_i
Equal
Ai
Bi Cin_i
Ki
Cout_(i 1)
August 2010 23
Below is a comparison of sum-addressed decoder with ordinary
decoder combined with a ripple carry adder (RCA) and carry look
ahead adder (CLA). A significant delay and area improvement is
achieved.
August 2010 24
Bit-Line Conditioning Circuits
August 2010 27
Isolation Devices
sense sense
Regenerative
Feedback
August 2010 28
Column Multiplexers
The SRAM is physically organized by 2n-k rows and 2m+k
columns.
August 2010 29
Tree Decoder Column Multiplexer
B0 B7 B0 B7
A0
A0
A1
A1
A2
A2
bit bit
To sense Amps and Write Circuits
August 2010 30
It is possible to implement the multiplexer such that data is
passed trough a single transistor, while column decoding takes
place concurrently with row decoding, thus not affecting delay.
A1 A0
B0 B1 B2 B3
August 2010 Y 31
DRAM Dynamic RAM
Store their charge on a capacitor rather than in a
feedback loop
Basic cell is substantially smaller than SRAM.
To avoid charge leakage it must be periodically read and
refresh
It is built in a special process technology optimized for
density
Offers order of magnitude higher density than SRAM but
has much higher latency than SRAM
August 2010 32
bit
A 1-transistor (1T) DRAM cell consists
word
of a transistor and a capacitor.
x
Ccell Cell is accessed by asserting the word-
line to connect the capacitor to the bit-
line.
August 2010 34
Like SRAMs, large DRAMs are divided into sub-arrays, whose size represents
a tradeoff between area and performance. Large sub-arrays amortize sense
amplifiers and decoders among more cells but are slower and have less swing
due to higher capacitance of word and bit lines.
bit0 bit1 bit511
word0
word1
Bit-line capacitance is far
larger than cell, hence
voltage swing V during
read is very small and
sense amplifier is used.
word255
August 2010 35
Open bit-line architecture Is useful for small DRAMs. It has dense layout
but sense amps are exposed to differential noise since their inputs come
from different sub-arrays, while word line is asserted in one array.
August 2010 36
Sub-array 1
Word-Line
Decoders
Word-Line
Decoders
Sense
Amps
Open Bit-Line
Architecture
Word-Line
Decoders
Word-Line
Decoders
Sub-array 2
August 2010 37
Folded Bit-Line Architecture
Sense
Amps
Word-Line
Decoders
Word-Line
Decoders
Sense
Amps
August 2010 38
Polysilicon Word-Line
Sense Amp
Metal Bit-Line
n+ Diffusion
Word-Line Bit-Line Contact
Decoder
Capacitor
Word-Line
Decoder Word-Line
Decoder
Word-Line
Decoder
Sense Amp
August 2010 39
DRAM Sense Amp
August 2010 40
VDD
Bit
VDD/2
Bit
VDD
VDD/2
Vn
Vp
0
August 2010 41