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Here
2n = m
Table
Control input Data input Multiplexer
(n) (2n) = m
1 21=2 2 - to 1
2 22=4 4 - to 1
3 23=8 8 - to 1
4 24=16 16 - to - 1
2-to-1 Multiplexer
Truth table
Data input Control Output
input (S0) (Q)
D0 D1
x y 0 X
x y 1 y
Circuit Diagram
Q D0 S 0 D1 S 0
4-to-1 Multiplexer
Truth table
Data input Control input
Output
D0 D1 D2 D3 S1 S0 (Q)
w x y z 0 0 w
w x y z 0 1 x
w x y z 1 0 y
w x y z 1 1 z
Circuit Diagram of 4-to-1 Mux
Q D0 S0 S1 D1 S0 S1 D2 S 0 S1 D3 S0 S1
8-to-1 Multiplexer
Circuit Diagram
Truth table
D 0 0 D
D 1 D 0
Where, D = 0 (or) 1
Circuit Diagram
D S0
D S0
1:4 Demultiplexer
Q D S 0 S1 D S 0 S1 D S 0 S1 D S 0 S1
Circuit Diagram
Truth table
Data Select Inputs Outputs
Input
D S1 S0 Y3 Y2 Y1 Y0
D 0 0 0 0 0 D
D 0 1 0 0 D 0
D 1 0 0 D 0 0
D 1 1 D 0 0 0
1-to-8 Demultiplexer
Circuit Diagram
Truth table
Assignment:
Draw circuit diagram and write the truth
table of 1:8 Demultiplexer and 1:16
Demultiplexer.
Applications
A very common application for this type of circuit is found
in computers, where dynamic memory uses the same
address lines for both row and column addressing. A set of
multiplexers is used to first select the row address to the
memory, then switch to the column address
Decoder
Where,
A Select line
D Output line
Fig. 2-to-4 line decoder
Where,
A Select line
D Output line
Truth table
8 to - 3 encoder