Documente Academic
Documente Profesional
Documente Cultură
Period 3 - 2007
Catharina Logothetis
Lecture 10
Last time, we talked about:
Channel coding
Lecture 10
Today, we are going to talk about:
Another class of linear codes, known as
Convolutional codes.
Lecture 10
Convolutional codes
Convolutional codes offer an approach to error control
coding substantially different from that of block codes.
A convolutional encoder:
encodes the entire data stream, into a single codeword.
does not need to segment the data stream into blocks of fixed
size (Convolutional codes are often forced to block structure by periodic
truncation).
is a machine with memory.
This fundamental difference in approach imparts a
different nature to the design and evaluation of the code.
Block codes are based on algebraic/combinatorial
techniques.
Convolutional codes are based on construction techniques.
Lecture 10
Convolutional codes-contd
A Convolutional code is specified by
three parameters (n, k, K) or (k/ n, K)
where
Rc k/n is the coding rate, determining the
number of data bits per coded bit.
In practice, usually k=1 is chosen and we
assume that from now on.
K is the constraint length of the encoder a
where the encoder has K-1 memory
elements.
There is different definitions in literatures for
constraint length.
Lecture 10
Block diagram of the DCS
Channel
i
Codeword sequence
U i u 1 i ,. .,u ji ,. .,u ni
Branch wo rd ( n coded bits)
Lecture 10
A Rate Convolutional encoder
u1 u1
u1 u2 u1 u 2
t3 1 0 1 0 0
t4 0 1 0 1 0
u2 u2
Lecture 10
A Rate Convolutional encoder
m(101
) Encoder
U(
1110
00
10
1)
1
Lecture 10
Effective code rate
Initialize the memory before encoding the first bit (all-
zero)
Clear out the memory after encoding the last bit (all-
zero)
Hence, a tail of zero-bits is appended to data bits.
Lecture 10
Encoder representation
Vector representation:
We define n binary vector with K elements (one
vector for each modulo-2 adder). The i:th element
in each vector, is 1 if the i:th stage in the shift
register is connected to the corresponding modulo-
2 adder, and 0 otherwise.
Example:
u1
g1(111
)
m u1 u 2
g2 (101
)
u2
Lecture 10
Encoder representation contd
Impulse response representaiton:
The response of encoder to a single one bit that
goes through it.
Example: Branch word
Register
contents u1 u2
1010
1
I
snpu
:
equ
100
0110
0
Os:
1equ
10
1
ut
1 1 p
0011
1
Input m Output
1 1 10 1
0 00 00 00
1 1 10 1
Modulo-2 sum: 1 10 00 10 1
Lecture 10
Encoder representation contd
Polynomial representation:
We define n generator polynomials, one for each
modulo-2 adder. Each polynomial is of degree K-1 or
less and describes the connection of the shift
registers to the corresponding modulo-2 adder.
Example:
g
(
X
1
)(
1
g
0
)(
g1
)
.
X(
1
)
g
.
1 2X
2
1
2
X
X
g
(
X
2
)(
2
g
)(
01
2
)
g
.
X(
2
)
g
.
2X
2
12
X
The output sequence is found as follows:
U
(
X
)
m
(
X)
g
(
X
)
i
1 n
m
(
X
)
g
(
w
X
)
2
Lecture 10
Encoder representation contd
In more details:
m
(
X
)
g
(
X
)
1
(
1
X
2
)
1
X
2
X
)
3
1
(
X
X
4
X
m
(
X
)
g
(
X
2
)
(
1
X
2
)
1
X
2
)
1
X4
(
m
(
X
)
g
(
X
)
1
1
X
2
0
.
X
X
3
X4
m
(
X
)
g
(
X
2
)
1
0
.
X
2
0
.
X
3
0
.
X
X4
U
(
X
)
(
1
,
1
)
(
1
,
0
)
X
(
0
,
0
)
X
2
(
1
,
0
)
X
3
(
1
,
14
)
X
U
110
00
1
11
Lecture 10
State diagram
A finite-state machine only encounters a
finite number of states.
State of a machine: the smallest amount
of information that, together with a
current input to the machine, can predict
the output of the machine.
In a Convolutional encoder, the state is
represented by the content of the
memory.
K 1
Hence, there are 2 states.
Lecture 10
State diagram contd
A state diagram is a way to represent
the encoder.
A state diagram contains all the states
and all possible transitions between
them.
Only two transitions initiating from a
state
Only two transitions ending up in a state
Lecture 10
State diagram contd
S1 01 0/10
1/01
0/01
S3 11 1/10
ti ti 1 Time
Lecture 10
Trellis contd
A trellis diagram for the example code
Input bits Tail bits
1 0 1 0 0
Output bits
11 10 00 10 11
0/00 0/00 0/00 0/00 0/00
1/11 1/11 1/11 1/11 1/11
0/11 0/11 0/11 0/11 0/11
1/00 1/00 1/00 1/00 1/00
0/10 0/10 0/10 0/10 0/10
1/01 1/01 1/01 1/01 1/01
0/01 0/01 0/01 0/01 0/01
t1 t2 t3 t4 t5 t6
Lecture 10
Trellis contd
t1 t2 t3 t4 t5 t6
Lecture 10