FET

Prepared by Nidhi Patel

Advantages of FET over BJT
1. Unipolar device i. e. operation depends on only
one type of charge carriers (h or e)
2. Voltage controlled Device (gate voltage controls
drain current)
3. Very high input impedance (109-1012 )
4. Source and drain are interchangeable in most
Low-frequency applications
5. Low Voltage Low Current Operation is possible
(Low-power consumption)
6. Less Noisy as Compared to BJT
7. No minority carrier storage (Turn off is faster)
8. Very small in size, occupies very small space in
ICs
 FET construction
major part of the structure is the n-type material that forms the
channel between the embedded layers of p-type material
The n-type channel is connected through an ohmic contacts
drain (D) and source (S)
The two p-type materials are connected together and to the
gate (G) terminal
In the absence of any applied potentials the JFET has two p-n
junctions under no-bias conditions
 Working of FET

Water analogy of FET

JFET in the VGS = 0 V and VDS > 0 V.

Varying reverse-bias potentials across the p-n
junction of an n-channel JFET.
Characteristic of FET

Pinch-off (VGS = 0 V, VDS = VP)

ID versus VDS for VGS = 0 V

Regions in FET
VGS < 0
Break down regions for VGS < 0
Transfer characteristics
Working of FET
FET small signal model low frequency
iD= f(VGS,VDS)
id = gm vgs+ (1/rd)vds
1/rd = drain conductance
Gate current is zero hence G to S junction is represented as open
circuit and no current is drawn from FET, the reason is i/p
resistance is very high
o/p resistance is rd
Small signal model for sinusoidal i/p of FET consider RMS
values of Vgs, Vds and Id
gm vgs = Vgs
is amplification factor and = gm rd
FET small signal model high frequency

Since Cds is small compared to Cgs, the drain-source

capacitance may be ignored in most analysis and design
situations
FET fixed biasing

If the resistance rd is sufficiently large

(at least 10;1) compared to RD,

AC equivalent ckt
 VDD

FET self bias

AC equivalent ckt
FET voltage divider bias

AC equivalent ckt
MOSFET

Figure:nChannelEnhancementMOSFETshowingchannellengthLandchannelwidthW.
Depletion-type MOSFET.
n-Channel depletion-type MOSFET with
VGS = 0V and an applied voltage VDD.

Symbols for
(a) n-channel depletion-type MOSFETs
and
(b) p-channel depletion-type
MOSFETs.
Drain and transfer characteristics for an n-
channel depletion-type MOSFET
ENHANCEMENT-TYPE MOSFET

n-Channel enhancement-type MOSFET.

Channel formation in the n-channel
enhancement type MOSFET

Change in channel and depletion

region with increasing level of VDS
for a fixed value of VGS
Drain and transfer characteristics of an n-
channel enhancement-type MOSFET
Symbols for
(a)n-channel enhancement-type
MOSFETs and (b) p-channel
enhancement-type MOSFETs
CD amplifier

AC equivalent ckt
 FET Mid-frequency Analysis: VDD VDD

A common source (CS) amplifier is shown R1

RD

to the right. io
D
Co
The mid-frequency circuit is drawn as follows: ii G
+
the coupling capacitors (Ci and Co) and the Rs
+ Ci S
+
RL vo
bypass capacitor (CSS) are short circuits vs R2
vi
short the DC supply voltage (superposition) _ RSS CSS _

replace the FET with the hybrid-p model _

The resulting mid-frequency circuit is shown below.

io
is ii g d

+ + +
vs RTh vi = vp rd RD RL vo
gmvp
_ _ _

s s
mid-frequency CE amplifier circuit

Analysis of the CS mid-frequency circuit above yields:

vo vo Zi
A vi = = -g m R 'L , where R L' = rd R D R L A vs = = A vi
vi vs R s + Zi
vi io Zi
Zi = = R Th , where R Th = R 1 R 2 AI = = A vi
ii ii RL
vo po
Zo = = rd R D AP = = A vi A I
io seen by R L
pi
 VDD VDD
FET Amplifier Configurations and
RD
Relationships:
R1
io
D
Co
CS CG CD
ii G
Rs +
' ' g m R 'L
+
+ Ci S
RL vo A vi -g m R L g mR L
vs vi
R2 1 g m R 'L
C SS _
_ RSS

_ R 'L rd R D R L rd R D R L R SS R L
Common Source (CS) Amplifier 1
Zi R Th R SS R Th
ii S D
io gm
Rs Co
+ Ci
G + 1
+
vi RSS
RD
Zo rd R D rd R D R SS
vs
_
RL vo
gm
R1
_
_
C2 R2 VCC
Zi Zi Zi
A vs A vi A vi A vi
Common Gate (CG) Amplifier
R
s + Z i R
s + Z i R
s + Z i

Z Z Z
VDD VDD
AI A vi i A vi i A vi i
R1
RL RL RL
D
AP A vi A I A vi A I A vi A I
ii G

+
Rs + Ci S io where R Th = R 1 R 2
vs R2 Co +
vi
_ R SS RL vo Note: The biasing circuit is the same for each amp.
_ _

Common Drain (CD) Amplifier (also called source follower)

CMOS
A very effective logic circuit can be established by constructing
a p-channel and an n-channel MOSFET on the same substrate
This referred to as a complementary MOSFET arrangement
(CMOS) that has extensive applications in computer logic design
Features: The relatively high input impedance, fast switching
speeds, and lower operating power levels
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