SystemVerilog Assertions (SVA)

What are assertions? Why use

them?
Assertions are a set of rules that define required
timing between specified signals in the design

Verifies that the design does what it is suppose to

do

Guards from misuse of design component (other

users)

Enables fast detection of errors (early in simulation)

As cover point, shows that the design has reached

desired states
Immediate assertions
Fast way to define required logical conditions in
the design
Executed from a procedural block
Immediate assertions are useful for checking combinational
expression.
Similar to if and else statement but with assertion control.
Immediate assertions follow simulation event semantics for
their execution and are executed like a statement in a
procedural block.

always @(posedge clk)

if (state == REQ)
assert (req1 || req2)
$display("%m passed");
else
$error("assert failed at
Concurrent assertions contd

Boolean expession: basic building block of

assertions.

Evaluate sampled value of variables used

0,X,Z interpret as false
Excludes certain
types(time,string,class,asociative/dynamic
arrays,real,short real,real)
Variables used must be static
Excludes these operators(+=,-=,i++,i--,++i etc)
Concurrent assertions contd
Sequences: Sequences regular expressions
A list of SV boolean expressions in linear order of increasing time
Boolean test for whether a signal matches a given sequence or not
Assumes an appropriate sampling clock and start/end times
if all samples in the sequence match the simulation result then the assertion
matches

Describe sequences
Uses properties and sequences as main building
blocks

property req_ack;
@(posedge clk) req |=> ack;
endproperty

assert_req_ack: assert property

(req_ack);
|-> operator

The |-> operator states that if sequence req

occurs, sequence ack should be true with
overlap time

property req_ack;
@(posedge clk) req |->
ack;
endproperty

clk

req

ack
|=> operator
The |=> operator states that if sequence req
occurs, sequence ack should be true on next
time state

property req_ack;
@(posedge clk) req |=>
ack;
endproperty

clk

req

ack
##(num) operator

The ##(num) operator states that the sequence

on the right hand of the operator should be true
num cycles after the sequence on the left hand
is true
property req_ack;
@(posedge clk) req |=> ##1
ack;
// @(posedge clk) req |->
##2 ack; (equal)
endproperty
clk

req

ack
##[start:end] operator

The ##[start:end] operator states that the

sequence on the right hand of the operator
should be true at some clock tick between start
property
and endreq_ack;
number of cycles after the sequence on
@(posedge
the left hand clk) req |=> ##[1:2] ack;
endproperty

clk req followed by 1

or 2 cycles of ack
req

ack
[*] operator Consecutive Repetition
a[*N] //repeat a, N times consecutively
a ##1 b ##1 b ##1 b ##1 c same as a## 1 b[*3]
##1 c
A[*N:M] // repeat a at-least N and as many as M
times consecutively
The [*(num)] operator states that the sequence
on the right hand of the operator should repeat
property req_ack;
for num clock ticks
req followed by 3
@(posedge clk) req |=> ack[*3];
endproperty cycles of ack

clk

req

ack
$ operator
The $ operator is used to indicate an unbounded
event
a[*N:$] //repeat a unknown number of times
but at least N times
property req_ack;
@(posedge clk) req |=> ack[*2:$];
endproperty
req followed by at
least 2 cycles of ack
clk (may be forever)

req

ack
sequences
Sequences describe a sequence of timed events
synchronous to a reference clock
sequence req_data_finish_seq;
req ##1 data[*2:4] ##2 finish;
endsequence

sequence
start req followed by 2-4
cycles of data
clk
followed (after 2
sequence
req end cycles) by finish

data

finish
 sequences (cont)
sequence seq1; sequence seq2;
a ##1 b[*2] ##1 c; d ##2 e;
endsequence endsequence
property p1;
@(posedge clk) seq1 |=> Assertion fired
seq2;
endproperty (checking seq2)
seq1 start |=>
clk
Assertion passed
a
seq1 end
b
seq2 start
c
seq2 end
d
e
-> operator

The -> operator states a non-consecutive repetition

b[->N] // goto the Nth repeat of b. Delay in-between bs need

not be ##1

Example :

a ##1 b[->4] ##1 c //a followed by exactly four not

necessarily consecutive bs with last b followed next tick by
c

Note: VERY IMORTANT c have to follow immediately after

the last b.

a ##1 b[->3:4] ##1 c //a followed by at least 3 at most

4 bs before c. Last b followed next tick by c
-> operator
property p1; property p2;
@(posedge @(posedge
clk) clk)
a |=> a |=> c[-
b[*2]; >2];
endproperty endproperty

clk

c
Concurrent assertions

Unlike immediate assertions, describe behavior that spans

across time
clock based
= operator

b[=N] ##c //repeat b, N times (not necessarily

consecutive) followed some time by c

Example :

a ##1 b[=4] ##1 c //a then exactly 4 repeats of b then c

Note: VERY IMORTANT c doesnt have to follow immediately

after the last b.

If it is 5th b before C then fails

a ##1 b[=3:4] ##1 c //a then at least 3 at most 4

repeats of b then c
->/= operator

sequence seq1; a followed by 2-10 cycles

a ##1 b[->2:10] (not-necessarily-consecutive) in
##1 c; which b is true, one cycle
endsequence after last b, c is true

sequence seq1; a followed by 2-10 cycles

a ##1 b[=2:10] (not-necessarily-consecutive) in
##1 c;
which b is true,
endsequence
somewhere after last b, c
is true