Documente Academic
Documente Profesional
Documente Cultură
Joe Bungo
Applications Engineer
ARM University Program
1
Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
System Design
Development Tools
2
ARM Ltd
Founded in November 1990
Spun out of Acorn Computers
Initial funding from Apple, Acorn and VLSI
3
ARMs Activities
Connected Community
Development Tools
Software IP
Processors
memory
System Level IP:
Data Engines
SoC
Fabric
3D Graphics
Physical IP
4
ARM Connected Community 700+
5 5
Huge Range of Applications
IR Fire
Detector
Utility Exercise
Machines Intelligent
Intelligent toys Meters Energy Efficient Appliances
Vending
Tele-parking
6
Worlds Smallest ARM Computer?
Battery Solar Cells
Wireless Sensor Network
Sensors, timers
A B C
Processor, SRAM and PMU
7
Worlds Largest ARM Computer?
8
From 1mm3 to 1km3
1mm3 1km3
10 $1000
9
Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
System Design
Development Tools
10
ARM Cortex Processors (v7)
Cortex-M0
12k gates...
11
Cortex family
Cortex-A8 Cortex-R4 Cortex-M3
Architecture v7A Architecture v7R Architecture v7M
MMU MPU (optional) MPU (optional)
AXI AXI AHB Lite & APB
VFP & NEON support Dual Issue
12
Relative Performance*
2500
2000
Max Frequency (Mhz)
1500
1000
500
0
Cortex- Cortex- Cortex-A9
ARM7 ARM926 ARM1026 ARM1136 ARM1176 Cortex-A8
M0 M3 Dual-core
Max Freq (MHz) 50 150 184 470 540 610 750 1100 2000
Min Power (mW/MHz) 0.012 0.06 0.35 0.235 0.36 0.335 0.568 0.43 0.5
13
Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
14
ARM and Thumb Performance
30000
25000
20000
Dhrystone 2.1/sec
@ 20MHz
15000 ARM
Thumb
10000
5000
0
32-bit 16-bit 16-bit with
32-bit stack
15
The Thumb-2 instruction set
Variable-length instructions
ARM instructions are a fixed length of 32 bits
Thumb instructions are a fixed length of 16
bits
Thumb-2 instructions can be either 16-bit or
32-bit
16
Cortex-M Programmers Model
Main
Fully programmable in C
r0
r1
xPSR
17
Cortex-M3 Processor Privilege
ARM Cortex-M3
Privileged
Aborts
Supervisor Interrupts
Reset
Handler Mode
OS
User Non-Privileged
Memory
18
Cortex-M3 Interrupt Handling
One Non-Maskable Interrupt (INTNMI) supported
1-240 prioritizable interrupts supported
Interrupts can be masked
Implementation option selects number of interrupts supported
Nested Vectored Interrupt Controller (NVIC) is tightly coupled with processor core
Interrupt inputs are active HIGH
INTNMI
Cortex-M3
19
Cortex-M3 Exception Handling
Reset : power-on or system reset
NMI : cannot be stopped or preempted by any exception other than reset
Faults
Hard Fault : default Fault or any fault unable to activate
Memory Manage : MPU violations
Bus Fault : prefetch and memory access violations
Usage Fault : undef instructions, divide by zero, etc.
SVCall : privileged OS requests
Debug Monitor : debug monitor program
PendSV : pending SVCalls
SysTick Interrupt : internal sys timer, i.e., used by RTOS to periodically
check resources or peripherals
External Interrupt : i.e., external peripherals
20
Cortex-M3 Program Status Register
31 28 27 26 25 24 23 16 15 10 7 0
21
Conditional Execution
If Then (IT) instruction added (16 bit)
Up to 3 additional then or else conditions maybe specified (T or E)
Makes up to 4 following instructions conditional
ITTET EQ MOVEQ
Inst 1 ADDEQ
Inst 2
SUBNE
Inst 3
Inst 4 ORREQ
22
Classes of Instructions (v4T)
Load/Store
Miscellaneous
Data Operations
Change of Flow
MOV PC, Rm
Bcc
BL
BLX
23
Data processing Instructions
Consist of :
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons: CMP CMN TST TEQ
Data movement: MOV MVN
24
Using a Barrel Shifter:The 2nd Operand
Immediate value
8 bit number, with a range of 0-255.
25
Single register data transfer
LDR STR Word
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load
Syntax:
LDR{<cond>}{<size>} Rd, <address>
STR{<cond>}{<size>} Rd, <address>
e.g. LDREQB
26
Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
System Design
Development Tools
27
Cortex-M3 Datapath
I_HRDATA Instruction
Decode
Address
Register Barrel
Incrementer Mul/Div
Bank Shifter
I_HADDR ALU
A ALU
Address
Register
Writeback
INTADDR
28
Cortex-M3 Pipeline
Cortex-M3 has 3-stage fetch-decode-execute pipeline
Similar to ARM7
Cortex-M3 does more in each stage to increase overall
performance
Instruction
Fetch
Decode & Multiply & Divide Write
(Prefetch)
Register Read
29
ARM10 vs. ARM11 Pipelines
ARM10
Branch Memory
ARM or
Prediction Shift + ALU
Thumb Reg Read Access Reg
Instruction Write
Instruction
Decode Multiply
Fetch Multiply
Add
FETCH ISSUE DECODE EXECUTE MEMORY WRITE
ARM11
Data Data
Address Cache Cache
1 2
30
Full Cortex-A8 Pipeline Diagram
13-Stage Integer Pipeline 10-Stage NEON Pipeline
F0 F1 F2 D0 D1 D2 D3 D4 E0 E1 E2 E3 E4 E5 M0 M1 M2 M3 N1 N2 N3 N4 N5 N6
Branch mispredict penalty
Replay penalty Instruction Execute and Load/Store NEON NEON register writeback
Integer register writeback
31
Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
System Design
Development Tools
32
An Example AMBA System
High Performance
APB
ARM processor UART
High
Bandwidth AHB Timer
APB
External
Bridge
Memory Keypad
Interface
33
Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
System Design
Development Tools
34
ARM Debug Architecture
Ethernet
Debugger (+ optional
trace tools)
35
Keil Development Tools for ARM
36
Keil Development Tools for ARM
37
University Resources
http://www.arm.com/support/university/
University@arm.com
38
Your Future at ARM
Graduate and Internship/Co-op Opportunities
Engineering: Memory, Validation, Performance, DFT, R&D, GPU and more!
Sales and Marketing: Corporate and Technical
Corporate: IT, Patents, Services (Training and Support), and Human
Resources
Keep in Touch!
www.arm.com/about/careers
39
TI Panda Board
OMAP4430 Processor
1 GHz Dual-core ARM
Cortex-A9 (NEON+VFP)
C64x+ DSP
PowerVR SGX 3D GPU
1080p Video Support
POP Memory
1 GB LPDDR2 RAM
USB Powered
< 4W max consumption
(OMAP small % of that)
Many adapter options
(Car, wall, battery, solar, ..)
40
Project Ideas Using Panda
OS Projects
OS porting to ARM/Cortex (TI OMAP)
MythTV system
Super-Panda stack of Pandas as compute engine and task
distribution
Linux applications
41
Fin
42
Nokia N95 Multimedia Computer
OMAP 2420
Applications Processor
ARM1136 processor-based
SoC, developed using Magma
Blast family and winner of
2005 INSIGHT Award for Most
Innovative SoC
Symbian OS v9.2
Operating System supporting ARM
processor-based mobile devices,
developed using ARM RealView
Compilation Tools
ST WLAN Solution
Ultra-low power 802.11b/g WLAN
chip with ARM9 processor-based
MAC
44
Targeting community development
Wikis, blogs,
$149 Personally promotion of
> 1000 participants affordable community
and growing activity
Active &
technical Freedom to
community innovate
Addressing
Open access to
open source Instant access to
hardware community >10 million lines
documentation of code
needs
Opportunity Free
to tinker and software
learn
45
Fast, low power, flexible expansion
OMAP3530 Processor
Peripheral I/O
600MHz Cortex-A8
DVI-D video out
NEON+VFPv3
3 SD/MMC+
16KB/16KB L1$
256KB L2$ S-Video out
430MHz C64x+ DSP USB 2.0 HS OTG
32K/32K L1$ I2C, I2S, SPI,
48K L1D MMC/SD
32K L2
JTAG
PowerVR SGX GPU
Stereo in/out
64K on-chip RAM
Alternate power
POP Memory RS-232 serial
128MB LPDDR RAM
256MB NAND flash USB Powered
2W maximum consumption
OMAP is small % of that
Many adapter options
Car, wall, battery, solar,
46
And more On-going collaboration at BeagleBoard.org
Live chat via IRC for 24/7 community support
Links to software projects to download
Other Features
4 LEDs
3
USR0 Peripheral I/O
USR1
DVI-D video out
PMU_STAT
SD/MMC+
PWR
2 buttons S-Video out
USER USB HS OTG
RESET I2C, I2S, SPI,
4 boot sources MMC/SD
SD/MMC JTAG
NAND flash Stereo in/out
USB
Alternate power
Serial
RS-232 serial
47
Project Ideas Using Beagle
OS Projects
OS porting to ARM/Cortex (TI OMAP)
MythTV system
Super-Beagle stack of Beagles as compute engine and task
distribution
Linux applications
48