Documente Academic
Documente Profesional
Documente Cultură
VLSI
LABORATORY
Proper hardware
Proper software
Foundry or link up with some fab lab
Test facility
Purpose
DESIGN STEPS
SCHEMATIC
LAYOUT DESIGN
DRC
LAYOUT Vs SCHEMATIC
PARASITIC EXTRACTION
POST LAYOUT SIMULTION
List of Experiments
1. To generate layout for CMOS Inverter circuit and simulate it for verification.
2. To prepare layout for given logic function and verify it with simulations.
3. Introduction to programmable devices (FPGA, CPLD), Hardware Description
Language (VHDL), and the use programming tool.
4. Implementation of basic logic gates and its testing.
5. Implementation of adder circuits and its testing.
6. Implementation of J-K and D Flip Flops and its testing.
7. Implementation 4 to 1 multiplexer and its testing.
8. Implementation of 3 to 8 decoder and its testing.
9. Implementation of sequential adder and its testing.
10. Implementation of BCD counter and its testing.
11. Simulation of CMOS Inverter using SPICE for transfer characteristic.
12. Simulation and verification of two input CMOS NOR gate using SPICE.
13. Introduction to Block Diagram Mathod
14. Design of digital Logic using block diagram.
Project
Mini Project: VHDL/Verilog based mini project
with emphasis on design and implementation
into the group of maximum 3 students.
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+
Microwind
Microwind is a tool for designing and
simulating circuits at layout level. The tool
features full editing facilities (copy, cut, past,
duplicate, move), various views (MOS
characteristics, 2D cross section, 3D process
viewer), and an analog simulator
Tools from Microwind
Microwind
DSCH
Microwind3 Editor
Microwind 2D viewer
Microwind 3D viewer
Microwind analog simulator
Microwind tutorial on MOS devices
View of Silicon Atoms
Getting Microwind
Go to the website
http://www.microwind.net/document
Download the freeware version of the
microwind
Unzip the files in a Folder
Microwind Downloads
INTRODUCTION THE TOOL
User-friendly and intuitive
design tool for educational
use.
Layout
library
Editing icons
The student draws the masks One dot on the 2D, 3D views
of the circuit layout and grid is 5
lambda, or Simulation
performs analog simulation 0.175 m Access to
properties
simulation
Palette of layers
Active technology
Ion current
List of model
parameters
for BSIM4
Voltage
cursors
Memory effect due to
source capacitance
Our Approach
MOS DEVICE 1.
Traditional teaching : in-depth
explanation of the potentials, 2.
fields, threshold voltage, and
eventually the expression of
the current Ids
Our approach : step-by-step
illustration of the most
important relationships
between layout and
performance.
1. Design of the MOS
2. I/V Simulation
3. 2D view
4. Time domain analysis
3.
4.
Feature Size
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
Rules
E.g. = 0.090 m in 0.180 m process
Layout design rules:
For complex processes, it becomes difficult to
understand the intricacies of the fabrication process
and interpret different photo masks.
They act as interface between the circuit designer
and the process engineer.
Microwind Environment
Menu Command
2D 3D Views
Simulation Properties
Palette of Layers
Work Area
Active Layers
Current Technology
Design Rules
N- Well
r 101 r 102
N - Well
r201 Minimum N+ and P+ diffusion width 4
r 201 P+ Diff
N - Well
r 201 N+ Diff
r202 Between two P+ and N+ diffusions 4
r 202
P+ Diff
N - Well
r 202
N+ Diff
r203 Extra N-well after P+ diffusion 6
r 203
P+ Diff
r 203
N - Well
N+ Diff
r204 Between N+ diffusion and n-well 6
P+ Diff
N - Well
r 204
N+ Diff
r210 Minimum diffusion area 162
r 210 P+ Diff
N - Well
r 210 N+ Diff
r301 Polysilicon Width 2
Polysilicon
r 301
P+ Diff
N - Well
Polysilicon
r 301
N+ Diff
r302 Polysilicon gate on Diffusion 2
Polysilicon
r 302
P+ Diff
N - Well
Polysilicon
r 302
N+ Diff
r307 Extra Polysilicon surrounding Diffusion 3
Polysilicon
r 307
P+ Diff
r 307
N - Well
Polysilicon
r 307
N+ Diff
r 307
r304 Between two Polysilicon boxes 3
Polysilicon
r 304
P+ Diff
N - Well
Polysilicon
r 304
N+ Diff
r307 Diffusion after Polysilicon 4
Polysilicon
r 307 r 307
P+ Diff
N - Well
Polysilicon
r 307 r 307
N+ Diff
r401 Contact width 2
Contact
r 401
Polysilicon Contact
Metal/Polysilicon Contact
r404 Extra Poly surrounding contact 1
Contact
r 404 r 404
Polysilicon Contact
Metal/Polysilicon Contact
r405 Extra metal surrounding contact 1
Contact
Polysilicon Contact
Metal/Polysilicon Contact
r 405 r 405
r403 Extra diffusion surrounding contact 1
Polysilicon
r 403
P+ Diff
N - Well
Polysilicon
r 403
N+ Diff
r501 Between two Metals 4
Metal 1 Metal 4
r 501
Metal 2 Metal 5
r 501
Metal 3 Metal 6
r510 Minimum Metal area 162
Metal 1 Metal 4
r 510 r 510
Metal 2 Metal 5
r 510 r 510
Metal 3 Metal 6
r 510 r 510
Step 1: Select Foundary
Step 2: Select Foundary
Step 3: n+ Diffussion
Step 4: Polysilicon
Step 5: n+diff and Metal Contact
This Completes nMOS design