APEX Center - Overview

 Like the art of mountaineering, Semiconductor Technology is a very

practically oriented science with very high peaks that few can scale
 Working professionals in industry are at different levels of height in
terms of expertise
 High-end expertise is to be found only in very small pockets within
the industry and academia across the globe
 Due to fast pace of innovation, Industry and Academia need to
come closely together for pursuing Applied Research
 At BITS-RIT APEX Center, we will attempt to bring together top
experts from industry and academia to help the working
professionals attain global heights in professional excellence
 Applied research will be a key focus through close collaboration with
industry and top academic institutions
RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Goals

Applied Research
 PhD Program for working professional
Education & full time students
 Short Courses to meet specific  Projects sponsored by Indian & US
industry needs semiconductor Industry
 Structural Master’s degree  Active research collaboration between
program RIT & BITS faculty
 Exchange of researchers between RIT
& BITS

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Program for Professional Excellence
 A world-class education, training, and hands-on program offered in
Bangalore
 To upgrade skills of VLSI professionals and managers to the
world-class level
 Offered by the best faculty members and industry professionals
from India and across the world
 OLAB extension will be set up at the center in Bangalore with
state-of-the-art EDA tools
 Offered to professionals from Center Affiliates companies
 The program will consist of multiple courses and access to OLAB
 Each course will be a complete unit in itself with appropriate credits
awarded from BITS - Pilani
 Accumulation of enough credits and completion of a thesis will
entitle for a master’s degree from BITS
 Will be taught by some of the best faculty and Industry professionals
from India and abroad
RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 BITS-RIT Collaboration

 BITS will take ownership in setting up the center, the labs, the equipment
and the management responsibilities for the center. All investments towards
this will come from BITS
 BITS will also drive the Professional Excellence Program with involvement
from faculty from RIT as well as from across the world
 Award of degrees / certificates for Professional Excellence programs will be
managed by BITS
 RIT will play the lead role in Applied Research, particularly in the area of
RF, Analog and Mixed Signal Design with involvement from BITS faculty
and others in Industry
 Prof. P. R. Mukund, Director RAMLAB at RIT will be visiting Bangalore often
to supervise the research programs.
 At least one or more research associates from RAMLAB of RIT will be
located in Bangalore to carry on with the applied research work.
 PhD degrees may be awarded by RIT and BITS jointly or separately
depending on the nature of association of the lead researchers
 BITS and RIT will jointly promote the center

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Course Structure

 Each course will normally be about 20-30 people and will

have a tuition fee of about INR 10K – 30K per course per
student (including access to OLAB as well)
 These courses will be offered as
 intensive courses (10 to 30 hours of teaching over
a period of one, two or three weeks), or
 over a semester

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Corporate Sponsors
 Each interested company will become a Corporate Sponsor for the
Center with an annual fee of INR 75K – INR 200K based on their
employee strength
 Corporate Sponsors will also be able to provide input on courses
offered and choice of faculty members
 Corporate Sponsors will ensure that the Center remains world class
and dynamic
 Annual Corporate Sponsorship Fee
 Employee Strength < 50 : INR 75K
 Employee Strength 50-100 : INR 125K
 Employee Strength > 100 : INR 200K

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Corporate Sponsorship Benefits
 Professionals from Sponsor Companies will be given
preference in enrollment in these courses
 Representatives from sponsor Companies will be invited to be
a member of the Technical Advisory Board to guide the
Center to meet their specific needs and the needs of Indian
Semiconductor Industry.
 Professionals from their companies would be able to enroll for
an M. Eng. Degree from BITS and credit these courses
towards their degree program.
 Resources of the center will be extended for research and
development including supervision for Ph.D. programs.
Corporate Sponsor will be able to directly benefit from this
activity.

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Suggested List of Courses
VLSI Technology and Systems
Foundation Courses Hours Lab
Introduction to VLSI Technology 18 No
Fundamentals of ASIC design 30 Yes
Digital Design using Verilog 30 Yes
Design for Test 30 Yes
FPGA Design with Xilinx 30 Yes
Integrated Circuit Packaging 15 No
Principles of Logic Synthesis 30 Yes
Custom Layout of Integrated Circuits 30 Yes

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Suggested List of Courses …
VLSI Technology and Systems
Advanced Courses Hours Lab
Phase-Locked Loop Systems and Clock Gen 15 Yes
Circuits
Signal Integrity Analysis for Integrated Circuit 15 Yes
Interfacing
Advanced ASIC Physical Design 30 Yes
Advanced Static Timing Analysis 15 Yes
Circuit Modeling and Simulation 15 No
Advanced HDL Coding Techniques 15 Yes
RF Design 30 Yes
Low Power Design Techniques 15 No
Design of System Level Test Benches 15 Yes
RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Suggested List of Courses …
VLSI Technology and Systems

Programming Hours Lab

Perl Scripting for Electronic Design Automation 30 Yes

Embedded Systems, DSP and misc. hardware

engineering

Real-Time Programming and Embedded 30 Yes

Systems Design

Embedded and Real-Time Linux 30 Yes

Practical Digital Signal Processing 30 Yes

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Other Possible Courses …
 In addition to the courses on VLSI, the scope
may be expanded to offer additional practice
oriented courses relevant for Industry
 Few Practitioner’s Courses identified
 Software Testing
 Technical Writing
 Embedded SW development
 Bio-Technology

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Value Proposition for Professionals

 Never before opportunity to enrich knowledge and

expertise where it matters
 Learn from best in class experts from all over the world,
right here
 Opportunity for people not having a Masters degree to
earn one through part-time route
 Opportunity for pursuing research through PhD
enrollments, while working
 A stronger alternative to distance learning options
available from US based universities

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Value Proposition for Industry

 Move up the value chain through skills and

expertise gained
 Possible avenue for better employee retention
 Compelling cost structure to try new ideas
 Excellent design infrastructure
 Instant access to university expertise on
fundamental knowledge

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Value Proposition for Faculty
 Chance to contribute to India’s success –
especially for NRI industry professionals &
professors coming from overseas
 Chance for strategic relationship with Indian
University system
 Joint research programs with BITS and working
professionals from industry in India
 Better understanding of the emerging markets
 Opportunity for fulfilling the passion for teaching
 World class remuneration

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 Value Proposition for Academia
 Through continuous interaction and help from the top experts
participating in BITS-RIT APEX programs, academic curriculums at
the University will be constantly enhanced to keep pace with the
latest
 Some of the courses offered at BITS-RIT APEX center will be
beamed remotely to the university campuses through video
conferencing with an option for the students at the campus to enroll
against credits. BITS may consider extending such facilities to other
interested universities as well at a future date
 Plan to fund fundamental and applied research at the university with
the resources generated at the BITS-RIT APEX center
 Chance to contribute to growth of India’s semiconductor industry by
facilitating high end talent generation and applied research
programs

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY
 BITS - Pilani
OLAB (Oysters Lab)
VLSI DESIGN LABORATORY

Integrated efforts of BITS, BITS Alumni

and Industry Professionals

Birla Institute of Technology & Science

Pilani, Rajasthan
OLAB at BITS, Pilani RAMLAB
Rochester Institute of Technology
Rochester NY
OLAB - Industry Sponsors

Open Silicon

Mentor Graphics

CADENCE
SUN WIPRO
Microsystems
OLAB FACILITIES
 A powerful centralized compute server
farm for EDA tools in Layer 1
Sun Fire v250, NAS 3300 & SDLT320
 Sun Ray software
 EDA tools & user files
 Automatic tape back-up
 Number of powerful SUNSPARC workstations
as compute servers in layer 2 :
• 20 Ultra 2 Enterprise server-class workstations
• Computing share through Sun Grid Engine
 40 SUN THIN Clients as nodes in layer 3.
 Connected with 1.0 Gbps network
connectivity
 Tool Suite from MAGMA
(About 15 sets of licenses of back-end
design tools for mixed signal and a
complete package for RTL to GDS flow)
 Tool Suite From CADENCE
 Foundry access for fabrication of parts
 FPGA design infrastructure for prototyping
OLAB ACTIVITIES

• Students of M.E. Microelectronics for

conducting
laboratory sessions
• Students of First Degree Programme
for courses
in the area of VLSI Design
• To Facilitate Research activities
• To conduct short term courses for
Industry
Professionals
• To support entrepreneurs in
Technology
 A Sample list Dissertation projects

sign of CISC Microprocessor ( M68010 compatib

sign of Application Specific Instruction set Proc

text to speech conversion

sign of A/D and D/A converters

sign of switched capacitor circuits

sign of a CAD tool for synthesis of OPAMPs

Currently a Project on ZigBee
enabled wireless sensor network is
taken up with joint efforts of faculty,
students and BITS Alumni.
Master/Controller module Sensor/Slave module
Processor
Processor
Sensors
Host I/F & RF Circuitry
(Wireless interface
Peripherals transceivers) Circuits

Analog
RF Circuitry Processors and wireless
interface transceivers are the same for
Circuits (Wireless both the master and slave
modules.
(ADC/DAC) transceivers)
Sensor/Slave module
Processor

RF Circuitry Sensors
(Wireless interface
transceivers) Circuits

WIRELESS MESHED SENSOR NETWORK ARCHITECTURE

OLAB will support a full chip
design capability at BITS through
state-of-the-art EDA tools
RF/Analog/Mixed Signal Lab (RAMLAB)

RF/Analog/Mixed signal Laboratory (RAMLAB)

Dept. of Electrical Engineering
Building 9, 3rd Floor, Room 3271
Rochester Institute of Technology
Rochester, NY 14623
 RAMLAB - Overview
Semiconductor Research
Corporation
AMLAB specializes in developing cutting edge design
solutions for RF, analog and mixed signal circuits
People: Intel Corporation
Technology Used:
Research Faculty
0.25 um TSMC
Graduate Students CMOS National Science
0.25 um IBM CMOS Foundation
Distinguished Researcher
Harris
Equipment: Corporation
Unix Workstations with Cadence
Suite Eastman Kodak
Company
ATE with probe station, spectrum
analyzer & Network Analyzer for RF Kawasaki LSI
Characterization Industry Liaisons
Ph.D. Students LSI Logic
Anand Gopalan Sharmila Sridharan
Sripriya Bandi Mark Pude
Tejasvi Das Jeff Lillie RAMLAB
Rochester Institute of Technology
Rochester NY
RAMLAB - Current Projects

 Chip-Package Co-Design Of RF-Mixed signal

Microsystems

 Built in Self Test Strategies for RF/Mixed Signal

Systems

 High-speed circuit design and Characterization

 Mixed-Signal IC Design beyond 10 GHz

RAMLAB
Rochester Institute of Technology
Rochester NY
 Collaboration with Harris Corporation

Work with Harris Corporation

VDD
R1 Tunable Wideband LNA Design
LD
M3 RF Front end circuitry is designed to be either
M2 only narrowband or wideband.
R2
For military applications wherein frequency
M1
LG hopping is popular for secure communications,
the above mentioned circuitry is not suitable.
LS
LNA Schematic Objective: design tunable RF LNA with very wide
frequency range and very fine selectivity

Simulation Results

Simulation results summary

Noise Figure v/s frequency
LNA was fabricated on a
10mm^2 Chip using IBM’s
0.25um CMOS RF 6-metal layer
process
Input return loss S11 v/s frequency
RAMLAB
Rochester Institute of Technology
Rochester NY
 Chip-Package Co-Design

Chip-Package Co-Design of RF Microsystems

Research Objectives  Convert intricate analysis into a set of simple

design rules that can be used by the designer

 Make trade-off analysis simpler

“To analyze different functional blocks in a RF microsystem,
in the 2-5GHz range for Chip-Package Co-Design, and develop  Make intricate problems opaque
a software package that performs early analysis of various to the designer
functional blocks”  First Time Right
 Lower time to market

Accomplishments
Integrated Passive Design
Early Design Software Developed
Circuit Components Designed and for Chip-Package Co-Design – • Embedded Inductor on Si Substrates
Fabricated using IBM’s 0.25um ‘DREAM’
• Developed Inductor Library for Embedded
CMOS • Suited for ‘Early Design’ Process
• Low Noise Amplifier • Applications are diverse including Development of Design Rules& Methodologies
• Single Balanced Mixer RF, Mixed Signal, Digital and Power
• Design constraints of ESD protection circuitry
Distribution
• Low Phase Noise VCO • Vertically Integrated Designs Developed

G. Nayak, P.R. Mukund, “Chip-Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS

RAMLAB
VCO using embedded passives in a silicon package”, 17th International Conference on VLSI Design and
Rochester Institute of Technology
3rd International Conference on Embedded Systems, Mumbai, India, January 2004
Rochester NY
 DREAM: Digital-RF Early Analysis Methodology
Digital Pin
Placement
Mixed Signal
Analysis

A/D and
Op-Amp
Analysis

Design
Methodologies
RF Horizontal Passive
Modules Floor Planning Characterization
Power
Digital Distribution
Modules
RF Design
Inductor
RF
Digital Logic
Vertical Library 2D and 3D Analysis for
MEMS Integration Phase Noise Analysis for VCO &
Power Distribution Analysis
40
L1 off chip
L2 off chip
Sideband Analysis for Mixer
Quality Factor

35
L1 on chip
L2 on chip

Novel Design
30

Early Design Software –

25

Techniques 20

‘DREAM’
15

10
Inductor Libraries
for RF Design
5
Frequency(GHz)
0
0 2 4 6 8

Inductor Modeling
and Characterization

Vertically Integrated Designs

RAMLAB
(Si on Si)
Rochester Institute of Technology
Rochester NY
 Application Specific Reduced Order
Modeling Technique
Change in S11 Pin Functionality, Package
due to package RF Circuit RLC Models Proposed SiP Design Methodology

Krylov’s
Sub Space
Models

Application
Specific Reduced
Order Models SiP Design
Methodology
S-parameters comparison with and without
package parasitics RFIC Design

Model Reduction for power pin Original Model Reduction for signal pin
curve
Equivalent circuit model for ground pin Order: 27
S11 Order = 5
Original curve
Order = 27
Lw Rg Order: 7
Order = 6
Lg Cg
Order: 6
Order: 5

G. Nayak, C. Washburn, P.R. Mukund, “System in a Package Design of a RF Front End System using RAMLAB
Application Specific Reduced Order Models ”,Accepted at the 18th International Conference on VLSI Design Rochester Institute of Technology
and 4th International Conference on Embedded Systems, Calcutta, India, January 2005 Rochester NY
Built-In-Self Test (BiST) for RF
systems

Semiconductor Research
Corporation

RAMLAB
Rochester Institute of Technology
Rochester NY
 Motivation – RF Testing Challenges

Probe
s Very act of probing can
affect circuit performance
Access to RF core difficult
Si
Die
RF
RF Design
Testing
Passives

CHI
Factors affecting RF Circuit P

reliability Bond Wire

 Process Variations
 Tolerances of Package
Parasitics CHIPCARRIER

 Quality of Passives: soft faults RAMLAB

Rochester Institute of Technology
Rochester NY
 Current sensor for GHz applications
Stage 1: Sensing Resistor (Rs) +
Source Follower
Stage 2: Inverting Amplifier
Stage 3: Current Amplifying Cell
Requirements of a sensor
•High Bandwidth
•Low Sensitivity to process
variations
•High Dynamic Range
•High Sensitivity
DESIGN FEATURES
•Sensing Resistor – 7 Ω
•Feedback structure
•Reduction in number of Gain Stages
•Addition of bypass capacitor
RAMLAB
Rochester Institute of Technology
Rochester NY
BiST for LNA, Mixer, VCO

 Low real estate and power

overheads!!
 Similar techniques can be used
to quantify
 Output Match (S22 ), Gain (S21 ),
and Linearity (1dB compression)
of LNA
 Entire self-test can be carried
out in less than 20μs.
0.15 1.35
0.14 1.34

BiST output
1.9GHz LNA and BIST circuit 0.13
BiST Output

1.33
0.12
fabricated in IBM 0.25 micron 0.11
1.32
1.31
0.1 1.3
0.09 1.29
0.08 1.28
1.775 1.975 2.16 -22 -16 -13
S11 frequency S11 magnitude

RAMLAB
Rochester Institute of Technology
Rochester NY
 Self-Calibrating RF circuits

1 Inability to probe RFICs Limitations of existing RFIC

2
directly testing
Probe 010010101000
s 010101001000
111001000011
000010101000
010101011111

High Cost $$ Use of DSPs

Si
Die
RF
RF Design
Testing
Can detect
3 Limitations of Co-Design but not
Time Intensive correct faults
 Wide tolerance ranges of package
parasitics
 Dependence of E.S.D. protection on
Hence, a circuit topology
that dynamically self-corrects its
environmental conditions performance in the presence of
 Package portability process faults and package
parasitics is desired!
 Design time and cost
RAMLAB
Rochester Institute of Technology
Rochester NY
 Self-Calibration: Methodology

Sense Peak Detector

Amplifier

Sense current Amplify sensed Down-convert Map signal to

Start with
with minimally current signal to performance
nominal RF ckt
intrusive baseband metric
element

RF CIRCUIT

Dynamically modify Generate NO

Performanc
design parameters in baseband/digital
e metric
RF circuit signal to modify
ok?
design parameters

YES
Baseband 3
Signal
End
Processing
Calibration
Figure 3. Proposed Methodology for self- process
correction of input match.

 Self-correction on-the-fly  Robust -> Two-tonal approach

 Non-intrusive current sensing  Cuts down design cycle cost and

time
 Baseband processing
 Low overheads RAMLAB
Rochester Institute of Technology
Rochester NY
Self-Calibration: Results
S11 curves before
and after
calibration.

(a) when a parasitic

inductance of
1nH is added.

(b) when CGS of the

LNA transistor is
reduced by
10%.

S11 curves before and after calibration for the

weakest corner:
Ideal S11 =1.824 GHz
Parasitic inductance shifted it to 1.728 GHz
After calibration the input match aligned
itself at 1.817 GHz
RAMLAB
Rochester Institute of Technology
Rochester NY
LSI Logic: High-speed circuit design and
Characterization

 Collaborative effort with LSI for device

characterization in high-speed circuits.

 Current empirical models require that

every device size used in design has to be
fabricated and the data curve-fitted.

 Model scalability with respect to both device size and technology is

required.

 0.18um, 0.13um, 90nm & 65nm foundry and data access from LSI

RAMLAB
Rochester Institute of Technology
Rochester NY
Kawasaki: Mixed-Signal IC Design
beyond 10 GHz

 3-year project begins May 2005

 Switching noise dependencies on logic activity and

packaging

 High speed clock distribution in a large chip

 Simultaneous switching outputs and containment

strategies

 Analog and digital isolation in a SoC design

 Circuit techniques to monitor core noise

RAMLAB
Rochester Institute of Technology
Rochester NY
 Thank You

RAMLAB
Birla Institute of Technology & Science Rochester Institute of Technology
Pilani, Rajasthan Rochester NY