An Overview of Some

Microcontrollers/Microprocessors
for Embedded Systems

1
MCS-51 Family

2
 The 8051 8-bit Microprocessor/
Microcontroller Family (MCS-51)

(Intel, Philips, Atmel, Siemens, AMD, etc)

8051, 8751, 8031, 8052, 8752, 8032, Atmel

89ATC2051 (20 pins), Philips 80C552 (with
A/D converter and PWM), 8051XA (16 bits)

3
 8051 (old chip) Block Diagram

External Interrupts

Interrupt 4k 128 bytes Timer 1

Control ROM RAM Timer 2

CPU

OSC Bus
4 I/O Ports Serial
Control

P0 P2 P1 P3 TXD RXD
Addr/Data
4
8051 Internal Block Diagram

5
8051 I/O Pins for 40-Pin DIP Package

6
 8051 Family (8051, 8052, 802051, etc)
 The 8051 is a Single
Chip Computer or
microcontroller
Developed Initially by
Intel. It is one of the
most widely used
microcontroller chips in
the world.
 Other Companies have
binary-compatible
microcontrollers with
additional features.
 There are several versions
of the 8051 family. At the
lowest end there is a 20-pin
AT89C2051 microcontroller
chip from Atmel (cost : US$
3.00 !!!).
 IMPORTANT PINS:
Port 0 (acts as a multiplexed low byte address and
data bus for large external memory design).
 Port 1 – 8-bit R/W - General Purpose I/O
 Port 2 (act as the high byte of the address bus for
large external memory design).
 Port 3 – General Purpose I/O if not using any of the
internal peripherals (timers) or external interrupts.
PSEN (out): Program Store Enable, the read strobe to
external program memory (active low).
ALE (out): Address Latch Enable, to latch address
outputs at Port0 and Port2
 EA (in): External Access Enable, active low for
access external program memory locations 0 to 4K
 UART pins for serial I/O on Port 3
XTAL1 & XTAL2: Crystal inputs for internal
oscillator.
7
 Basic 8051 Characteristics
 4K bytes of internal ROM
 128 bytes of internal RAM:
• four register banks (0 - 3),
each containing R0 - R7 8-bit
registers.
• 16 bytes of bit addressable
area.
• 80 bytes of general purpose
memory.
 Four 8-bit I/O ports (P0 - P3).
 Two 16-bit timers/counters
 One serial receiver/ transmitter
(UART) interface.
 One instruction cycle = 12 clock
cycles (1us per instruction at 12
MHz clock)
 Five (2 external and 3 internal)
interrupt sources.
 Expandable to 64K external
code (program) memory
space.
 Expandable to 64K external
data memory space.
 Boolean instructions work
with one bit at a time.
 4 s for either an 8-bit multiply
or divide instruction. (Assume
a 12 MHz clock signal).
 On chip oscillator to generate
clock.
 One cycle 8-bit Multiply and
Divide Instructions – Very
Limited use 8
 I/O Port (P0 - P3) Structure (Cont.)

 One of the most useful features of the 8051 is

that it contains four I/O ports (P0 - P3).
• All ports are bidirectional (they can take inputs and can
provide output signals).
• Each port has an 8-bit latch, an output driver and an input
buffer (see next slide example of Port 3 pin)
• All ports have multiple functions (except P1).
• On RESET all the ports associated with latches are set to 1’s.
• The bit latch is represented as a D type flip-flop.
• When a bit latch is to be used as an input, a “1” must be
written to the corresponding latch by the program to
configure it as an input.
• An instruction can read the status of the latch (read latch
signal) and a different instruction can read the status of the
input pin signal (read pin signal).
9
 Port P3

8051 Port 3 Bit Latches and I/O Buffers 10

 Port P0

 Acts as a multiplexed data bus:

• Tristate bus with strong pull-ups.
• 8-bit instruction bus, strobed by PSEN.
• Low byte of address bus, strobed by ALE.
• 8-bit data bus, strobed by WR and RD.
• Port 0 may not be used as general purpose I/O
when being used as the address/data bus.
 3.2 mA outputs (about 8 LSTTL
loads).

11
 Port P1

 This is an I/O port only (it does not have

other functions like timer or interrupt)
 Input:
• 1 is written to the latch on RESET or by a program, the
pins are floating on high impedance.
• Any external device can alter the state which can be read
by reading the latches.
 Output:
• Directly 0 to 0 or 1 to 1, whatever, it will appear on the
corresponding pins.
 All bit latches have a fixed internal pullup
resistor.
 1.6 mA outputs (about 4 LSTTL loads).

12
 Port P2 and P3

 Port P2 operates similarly to port P1,

and with an alternate function as high
byte of address bus for external
program and data memory accesses.
• Port 2 may not be used as general purpose I/O
when being used as the address bus.

 Port P3 operates similarly to port P1,

but it also provides the alternate
functions (see next slide).

13
Port 3 Alternate Functions

14
 Read-Modify-Write Feature

 Some instructions that read a port read the latch

and others read the pin.

 The instructions that read the latch rather than

the pin are the ones that read a value, possibly
change it, and then rewrite it to the latch. These
are called “read-modify-write” instructions.

 The read-modify-write instructions are directed

to the latch rather than the pin. The objective is
to avoid a possible misinterpretation of the
voltage level at the pin (you can´t read and
modify an externally provided input signal if you
don´t have control over it)
15
 Read-Modify-Write Instructions
 The instructions listed below are read-modify-write
instructions.
ANL (logical AND, e.g. ANL P1, A)
ORL (logical OR, e.g. ORL P2, A)
XRL (logical EX-OR, e.g. XRL P3, A)
JBC (jump if bit = 1 and clear bit, e.g. JBC P1.1, LABEL)
CPL (complement bit, e.g. CPL P3.0)
INC (increment, e.g. INC P2)
DEC (decrement, e.g. DEC P2)
DJNZ (decrement and jump if not zero, e.g. DJNZ P3, LABEL)
MOV PX.Y, C (move carry bit to bit Y of Port X)
CLR PX.Y (clear bit Y of Port X)
SET PX.Y (set bit Y of Port X)

• When the destination operand is a port, or a port bit,

these instructions read the latch rather than the pin.
• If only examine P1.0, then read the pin e.g. MOV C, P1.0
16
 Memory Organization

Code/Data Space Notable Features

 Space for code/program is
separate from data  Registers & I/O ports
 Max of 64K of code and 64K are memory mapped.
of data space, using external
components  Stack resides in
internal RAM
 How does the hardware know
when it is an internal or  Parts of the RAM are
external access to ROM or bit-wise accessible.
RAM? – Use different
instructions for each case !!
MOV – Internal RAM
MOVC – ROM/EPROM
MOVX – External RAM

17
 Register Banks

 4 banks of registers (R0 to R7)

 The idea of ‘register banks’ permits fast and effective

‘context switching’ whereby separate sections of software
use a private set of registers independent of other sections
of software.

 Why? What does this mean? What uses does this

have?

18
 An Accumulator Architecture: the 8051
 8051 is an accumulator architecture (not a
“pure” one)
 There’s one register, the accumulator (ACCU),
that is both source and destination register of
most operations
ADD A,ADDRESSB ; A = A + Mem[ADDRESSB]

 Registers are 8 bits wide

• Special instructions
 add with carry
 subtract with borrow

 Despite their age, 8051-like chips are still often

used in calculators, digital clocks, VCRs, etc.

19
 8051 Registers and PSW

 ACC - accumulator
 B - used in multiply and divide
 PSW - Program Status Word
 SP - Stack Pointer
 PC Program Counter - not user accessible
 IP, IE (Interrupt Priority and Interrupt Enable)
 DPH and DPL (Data Pointer High and Low)
 PCON – Power Control Register
 SBUFFER and SCON – Serial Buffer and Serial Control Reg
 TH0, TL0, TH1, TL1 – (Timer High and Low 0 and 1)
 TCON and TMOD – Timer Control Reg and Timer Mode Reg

PSW: CY - Carry
AC – Aux. Carry (cy from b2 to b3 - BCD)
CY AC F0 RS1 RS0 OV - P
F0 – General Use Flag – no specific func
RS0,RS1 - Bank Select (4 banks or sets)
0 0 - 00h to 07h
OV - Overflow
0 1 - 08h to 0Fh
- User defined flag
1 0 - 10h to 17h
P - Parity
1 1 - 18h to 1Fh 20
 8051 Special Function Registers
and Bit-Addressable Memory

Special Function Registers Bit-Addressable Memory

 Registers appear in  16 Special Function

internal memory space
• Working registers
• Port data registers
• Peripheral control registers
 Addresses 80 - FF
• Above internal Data
memory
Registers are bit
addressable.
 Byte addresses 80, 88,
90, … F8
• Bit addresses 80 - FF
 16 bytes of internal Data
memory are bit
addressable.
 Byte addresses 20 to 2F
• Bit address 00 - 7F

21
 8051 Programmer’s Model

Program Memory(64K)
7 0
FFFF 7 0
FFFF
60 K
1000
External 64 K • All instructions
OR
External • Constant Data
0FFF (Using MOVC)
4K 0000
0000 Internal

if EA = HI if EA = LO

Data Memory(64K)
FF AND FFFF
SFRs (Using MOVX)
80 64 K
7F RAM External @R
00 @DPTR
Internal 0000
Direct
Direct , Register,
Reg. Indirect
22
 8051 Internal RAM
Address
00 Register Set 0
08 Register Set 1
10 Register Set 2
18 Register Set 3
20
Bit Addressable
28
30
38
RAM
40
48 +
50 stack
58
60
68
70
78
 Which set of 8 registers is being used depends on 2 bits in the
Program Status Word (PSW)
23
 8051 Special Function Registers (SFRs)
80 P0 SP DPL DPH PCON
88 TCON TMOD TL0 PL1 TH0 TH1
90 P1
98 SCON SBUF
a0 P2
a8 IE
b0 P3
b8 IP
c0
c8
d0 PSW
d8
e0 ACC
e8
f0 B
f8
Address
24
 8051 Programmer’s Model

7F SFRs
SFRs
Scratch Pad Area A8 * IE Interrupt Enable Ctr 1 FF

A0 * P2 Port 2 F0 *B
RAM
99 SBUF Serial Data Buffer
98 * SCON Serial Control E0 * ACC

90 * P1 Port 1 D0 * PSW
30
8D TH1 timer 1 High
Bit #00 7F OR 8C TH0 timer 0 High B8 * IP
Bit Addressable RAM 20.0 2F.7 8B TL1 timer 1 Low
20 8A TL0 timer 0 Low
R7 89 TMOD timer/counter Mode B0 * P3
Bank 3 Select Bank 88 * TCEN timer/counter control
18 R0
R7 with 87 PCON Power Control
Bank 2
10 R0 PSW.4 , .3 =
Bank 1 R7 83 DPH
08 R0 RS1, RS0 Data pointer DPTR
82 DPL
Bank 0 R7 81 SP Stack pointer
00 R0 80 * P0 Port 0

* = Bit Addressable
25
 8051 Assembly Code Example

ORG 440h ; Define Origin (ORG) for Data

Dat DB 0FFh ; Define Byte (DB) in Program Memory
Wait EQU 35 ; Associate Label to Constant (equate)
Myword DW 1234h ; Define Word (DW) in Program Memory
ORG 0 ; Define Origin (ORG) for Program
Start: MOV A,#2Ch ; Acc 2C
INC R2 ; R2 R2+1
SETB P0.7 ; Port 0 Bit 7 1
ADD A,Wait ;A Acc + M(35)
DEC @R0 ; M(R0) M(R0) - 1
LJUMP Finished ; PC Finished
Finished :
General Format
Label: Opcode dest,src ; Comments 26
 8051 Addressing Modes (1)
 Immediate - # Label or Number
MOV R6,#14 ; R6 14 10
MOV A, #CAh ; Acc CA 16
MOV DPTR,#loc ; DPTR value of symbol “loc”

 Direct - Label or Number

MOV PSW,R5 ; M(PSW) R5
MOV A,045h ; Acc M(45 16)

 Register - Rn
MOV R1,A ; R1 Acc
MOV B,R3 ;B R3

27
 8051 Addressing Modes (2)

 Register Indirect - @R0, @R1, @DPTR

MOV @R0,#250 ; M(R0) 250 10
MOV A,@R1 ;A M(R1)
MOVX @DPTR,A ; External data M(DPTR) A

 Register Indirect Indexed - @A+DPTR, @A+PC

MOVC A,@A+DPTR ; A ROM(A+DPTR)
MOVC A,@A+PC ;A ROM(A+PC)
JMP @A+DPTR ; PC (A+DPTR)

 Bit - bit number or label.bit or bit label

MOV C,IE.0 ; cy bit 0 of IE reg (EX0)
MOV C,EX0 ; same
SETB 07Fh ; Bit 7F 1
SETB 2F.7 ; same

28
 Subroutines

 8051 stack grows from low addresses to high addresses

 SFR SP (address 81H) points to top of stack, i.e., if you
push a value onto the stack, it will be stored at address
SP+1

 Be careful: SP is initialized to 07H, alternate register

banks 1, 2, and user bit vars occupy internal RAM
addresses 08H-2FH

 Special instructions:
• PUSH op
• POP op
• op must be specified using direct addressing!

29
 Parameter passing

 Options for parameter passing:

• In internal memory

• In registers. Not really useful, because registers are part of (and

thus as fast as) internal memory

• On stack. Also not really useful because push and pop

instructions allow only direct addressing. Necessary for
implementing recursive functions (but because stack is at most
128 bytes, recursion depth must be limited).

• In external memory. Disadvantages: (1) slow, (2) can only be

accessed via DPTR register

30
 Interrupt Sources in 8051 Family (non vectored)

 External Interrupt INT0 (B2h Address) – External pin that has to be

enabled (and also have its priority set) via software. Deviation address:
0003h

 External Interrupt INT1 (B3h Address) – Another external pin similar to

INT0. Deviaton address: 0013h
NOTE: INT0 and INT1 are pins of port P3 – more precisely P3.2 and P3.3.

 Internal Interrupt TIMER/COUNTER 0 – It is generated by TIMER_0 that is

an internal peripheral. Deviation address: 000Bh

 Internal Interrupt TIMER/COUNTER 1 – It is generated by TIMER_1 that is

an internal peripheral. Deviation address: 001Bh

 Serial Communication Interrupt – Generated by the internal serial

communications controller. Deviation address: 0023h

31
 Interrupt Control Bits

 Enable Interrupt (IE – address A8h)

IE EA - - ES ET1 EX1 ET0 EX0
BIT DDRESS AF - - AC AB AA A9 A8

EX0 – External Interrupt INT0

ET0 - Interrupt from TIMER/COUNTER_0
EX1 - External Interrupt INT1
ET1 – Interrupt from TIMER/COUNTER_1
ES - Interrupt from Serial Controller
EA - Enable All, that is, enable each individual enable to operate

 Interrupt Priority (IP – address B8h)

IE - - - PS PT1 PX1 PT0 PX0

BIT DDRESS - - - BC BB BA B9 B8

PX0 =0 – Low Priority; PX0= 1 – High Priority – Highest priority within group
PT0 =0 – Low Priority; PT0= 1 – High Priority
PX1 =0 – Low Priority; PX1= 1 – High Priority
PT1 =0 – Low Priority; PT1= 1 – High Priority
PS =0 – Low Priority; PS = 1 – High Priority – Lowest priority within group
32
 Interrupt Control Bits (cont)

 Timer Control – TCON (address 88h) - (part of this register is used to

control level interrupts or edge generated interrupts)
 IT0, IT1 = 0 = Level
 IE0, IE1 = 0 = Level, else (=1) Negative Edge

TCON * * * * IE1 IT1 IE0 IT0

BIT DDRESS * * * * 8B 8A 89 88
 TF1 – Timer 1 overflow flag. Cleared by processor upon vectoring to the interrupt
service routine.
 TR1 – Timer 1 control bit. If TR1=1, timer 1 runs. If TR1=0, timer 1 stops
 TF0 – Timer 0 overflow flag. Similar to TF1
 TR0 – Timer 0 control bit. If TR0=1, timer 0 runs. If TR0=0, timer 0 stops
 IE1 – External Interrupt 1 edge flag. Set when a valid falling edge is detected at pin
P3.3. Cleared by hardware when the interrupt is serviced.
 IT1 – Interrupt 1 type control bit. If IT1=1, interrupt 1 is triggered by a falling edge on
P3.3. If IT1=0, interrupt 1 is triggered by a low logic level on P3.3.
 IE0 – External Interrupt 0 edge flag. Set when a valid falling edge is detected at pin
P3.2. Cleared by hardware when the interrupt is serviced.
 IT0 – Interrupt 0 type control bit. If IT0=1, interrupt 0 is triggered by a falling edge on
P3.2. If IT0 = 0, interrupt 0 is triggered by a low logic level on P3.2.
33
 Interrupt Control Bits (cont)

 Timer Mode Register – TMOD (not bit addressable)

• Specifies the Operation Mode of a Timer

TMOD GATE C/T M1 M0 GATE C/T M1 M0

Timer One Timer Zero

 GATE – If GATE = 1, timer x will run only when TRx=1 and INTx = 1. If GATE=0, timer
x will run whenever TRx=1.

 C/T – Timer mode select. If C/T=1, timer x runs in counter mode taking its input from
Tx pin. If C/T=0, timer x runs in timer mode taking its input from the system clock.

 M1 – Mode selector bit 1. MSB of selector.

 M0 – Mode selector bit 0. LSB of selector.

34
 Interrupt Control Bits (cont)
 Timer 2 Control Register – T2CON

T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2

 TF2 – Timer 2 overflow flag. Will not be set if RCLK=1 or TCLK=1.

 EXF2 – Timer 2 external flag. EXF2 is set when a falling edge is detected on T2Ex and EXEN2=1.
This causes an interrupt, if the timer 2 is enabled.

 RCLK – Receive clock flag. When RCLK=1, the UART (if in mode 1 or 3) will use the timer 2
overflow frequency for the receive clock.

 TCLK – Transmit clock flag – When TCLK=1, the UART (if in mode 1 or 3) will use the timer 2
overflow frequency for the receive clock.

 EXEN2 – External enable flag – If EXEN2=1, a capture or reload will be caused by a falling edge
on T2EX. If EXEN2=0, external events on T2EX are ignored.

 TR2 – Timer run control bit – If TR2=1, the timer will run. If TR2=0, the timer will stop.

 C/T2 – Timer mode select – If C/T2=1, timer 2 will act as an external event counter. If C/T2=0, timer
2 will count processor clock cycles.

 CP/RL2 – Capture/Reload flag – If CP/RL2=1, detection of a falling edge on T2EX causes a capture
if EXEN2=1. If CP/RL2=0, detection of a falling edge on T2EX or an overflow causes a timer
reload if EXEN=1.

35
 Interrupts on MCS-51 Family

 At which Moment Are Interrupts Sampled by the Microcontroller ?

• Every S5P2 clock cycle of every machine cycle – See figure below
One Machine Cycle

S1 S2 S3 S4 S5 S6

S5P1 S5P2 S6P1 S6P2

• Once Sampled, an Interrupt will be accepted if:

• There isn´t another interrupt of same or higher priority being executed
• If the next machine cycle is the last cycle of an instruction
• If in the next cycle there is no RETI or any access to the interrupt registers IE
and IP.
• If the above conditions are followed, interrupt is accepted. In the following two
cycles the uP saves the PC in the Stack and loads the PC with the interrupt address.
36
 Basic Structure of a Program with Interrupts:
org 0000h ; beginning after RESET
ljmp BEGIN ; Go to BEGIN. Instructions below written in MEM
org 0003h ; INT0 interrupt address
nop ; If this int is used substitute nop and reti by
reti ; a long jump, the routine and an reti at the end.
org 000Bh ; TIMER_0 interrupt address
nop
reti
org 0013h ; INT1 interrupt address
nop
reti
org 001Bh ; TIMER_1 interrupt address
nop
reti
org 0023h ; SERIAL interrupt address (Receive + Transmit)
nop
reti
BEGIN: ; Begin of MAIN PROGRAM
--- ;
---
end ; Program END
37
 Example: Changing P1.0 and P1.1 Output Values
on Timer_0 and Timer_1 Interrupts
org 0000h ; Microcontroller RESET
ljmp BEGIN ; Goto BEGIN
;----------------------------------------------------------------------------------------------------
org 000Bh ; TIMER_0 interrupt address
cpl P1.0 ; Toggles output level of pin P1.0
mov TH0, #3Ch ; Load THIGH of TIMER_0 with initial value
mov TL0, #0AFh ; Load TLOW of TIMER_0 with initial value
reti ; Return from Interrupt for TIMER_0
;---------------------------------------------------------------------------------------------------
org 001Bh ; TIMER_1 interrupt address
cpl P1.1 ; Toggles output level of pin P1.1
reti ; Return from Interrupt for TIMER_1
;---------------------------------------------------------------------------------------------------
BEGIN: ; Begin of MAIN PROGRAM
mov TMOD, #21h ; Prog TIMER_0 - Mode1 / Timer_1 – Mode 2 (auto reload)
mov TH0, #3Ch ; Load THIGH of TIMER_0 initial value – part HIGH
mov TL0,#0AFh ; Load TLOW of TIMER_0 initial value – part LOW
mov TH1,#0CDh ; Load THIGH of TIMER_1 initial value – part HIGH
mov TL1,#0CDh ; Load TLOW of TIMER_1 initial value – part LOW
mov IE, #8Ah ; Programs Interrupt of both timers
mov IP, #08h ; Gives more priority to TIMER_1
setb TR1 ; Turns TIMER_1 on
setb TR0 ; Turns TIMER_0 on
------- ; Other program instructions
-------
end ; Program END

38