UNIT-4: MICROPROGRAMMED

CONTROL
1. Address Sequencing (4.2)
Routine
Subroutine
Subroutine Register
Conditional Branching
Mapping of Instruction with example
Address Sequencing
2. Micro programmed example (4.2)
Micro Instruction Format
3. Design and Implementation of Control Unit (4.3)
Decoding of Micro operations
Micro program Sequencer
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 4.2 Address Sequencing
• Routine
– Group of microinstructions stored in control memory
– Each computer instruction has its own micro
program routine to generate micro operations that
execute the instruction
• Subroutine
-Sequence of micro instructions used by other
routines to accomplish particular task
- Example subroutine to generate effective
address of operand for memory reference
instructions.
• Subroutine Register (SBR)
- Stores return address during subroutine call
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 4.2 Address Sequencing
Conditional Branching (Branch Logic)
• Provides decision making capabilities in CU
• Branching from one routine to another depends on status bit
conditions
• Status bits provide parameter info such as
– Carry-out of adder
– Sign bit of number
– Mode bits of instruction
• Info in status bits can be tested and actions initiated based on
their conditions: 1 or 0
• The status bits together with the field in the micro instruction
that specifies a branch address, control the conditional branch
decisions generated in the branch logic
• Unconditional branch
– An unconditional branch micro instruction can be implemented by
loading the branch address from control memory into the control
3
address register (CAR)
 4.2 Address Sequencing
Mapping of instructions with example
• Each computer instruction has its own
micro program routine stored in a given
location of the control memory
• Mapping
– Transformation from instruction code bits to
address in control memory where routine is
located is called mapping.

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 4.2 Address Sequencing
Example of Mapping
– Mapping 4-bit operation code to 7-bit address

OP-codes of Instructions
ADD 0000
AND 0001
LDA 0010 Control
memory
Mapping bits 0 xxxx 00 Address
0 0000 00 ADD Routine

0 0001 00 AND Routine

0 0010 00 LDA Routine

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 4.2 Address Sequencing
Address Sequencing - Selection of address for
control memory
• Address sequencing capabilities required in
control unit
– Incrementing CAR
– Unconditional or conditional branch, depending on
status bit conditions
– Mapping from bits of instruction to address for control
memory
– Facility for subroutine call and return

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 4.2 Address Sequencing
Instruction code

Mapping
logic

Status MUX 2 3 Multiplexers 4 1

Branch
bits logic select
Subroutine
Register
Control Address Register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address
Multiplexer Inputs
1. CAR Increment
2. JMP / Call
3. Mapping
4. Subroutine Return
 4.2 Microprogram Example
MUX
10 0
Computer AR
Configuration Address Memory
10 0 2048 x 16
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0
AC
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 4.2 Microinstruction Format
Computer instruction format
15 14 11 10 0
I Opcode Address

Four computer instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC  AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field

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4.2 Micro Instruction Format
Microinstruction Fields
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved

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4.2 Micro Instruction Format
Microinstruction Fields

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

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 4.2 Micro Instruction Format
Microinstruction Fields

Example of Micro instruction Format with three Micro operation Fields

DR  M[AR] with F2=100

PC  PC + 1 with F3=101

So the nine bits (F1,F2.F3 ) of micro operation fields are-:

000 100 101

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 Symbolic Microinstruction
 Sample Format Label: Micro-ops CD BR AD

 Label may be empty or may specify symbolic address

terminated with colon

 Micro-ops consists of 1, 2, or 3 symbols separated by commas

 CD one of {U, I, S, Z}
U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

 BR one of {JMP, CALL, RET, MAP}

 AD one of {Symbolic address, NEXT, empty}

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4.3 Design and Implementation of Control Unit
Decoding of micro operation Fields
microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

7 6 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0

AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR

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 4.3 Design and Implementation of Control Unit
Decoding of micro operation Fields
Decoding of Microinstruction Fields :

• F1, F2, and F3 of Microinstruction are decoded with a 3 x 8

decoder
• Output of decoder must be connected to the proper circuit to
initiate the corresponding microoperation
• F1 = 101 (5) : DRTAR
F1 = 110 (6) : PCTAR
Output 5 and 6 of decoder F1 are connected to the load input
of AR (two input of OR gate)
• Multiplexer select the data from DR when output 5 is active
Multiplexer select the data from PC when output 5 is inactive
• Arithmetic Logic Shift Unit
Control signal of ALU in hardwired control
Control signal will be now come from the output of the 15
decoders associated with the AND, ADD, and DRTAC.
 4.3 Microprogram Sequencer (imp)

• Microprogram Sequencer selects the next address in Control

in control memory for which microinstruction is to be fetched

• The basic components of a microprogrammed control unit are:

-Control Memory
-Circuits that selects the next address
(The address selection part is called Microprogram
sequencer)

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4.3 Microprogram Sequencer
External
(MAP)

L
I 3 2 1 0
Input Load
I0 S1 MUX1 SBR
logic
T1 S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...
MUX1 1Inputs
0. CAR (Increment)
1. JMP / Call
2. Mapping
3. Subroutine Return
4. 3 Input Logic for Microprogram
Sequencer
1 L L(load SBR with PC) for
From I MUX2 Test
CPU S T subroutine Call
BR field Input
Z Select I0 logic S0 for next address
of CM I1
S1 selection

CD Field of CM

Input Logic
I1 I0 T Meaning Source of Address S1 S0 L

000 In-Line CAR+1 0 0 0

001 JMP CS(AD) 0 1 0
010 In-Line CAR+1 0 0 0
011 CALL CS(AD) and SBR <- CAR+1 0 1 1
10x RET SBR 1 0 0
11x MAP DR(11-14) 1 1 0

S1 = I1
S0 = I0I1 + I1’T
L = I 1’ I0T