Detalii privind circuitele FPGA (Field Programmable Gate Array).

1. Introducere.
Obiective urmarite:
-principii,
-implementare,
-programarea circuitelor logice configurabile din punctul de vedere al
proiectarii celulelor, cat si al strategiei de interconectare
FPGA reprezinta circuite integrate care pot fi programate de catre
utilizator.
FPGA contin:
-functii versatile,
-interconexiuni configurabile,
-interfete de I/E adaptabile conform specificatiilor utilizatorului.
Fig.1. Structura uzuala a unui circuit FPGA
 Fig.2 Implementarea unei functii XOR cu 3 intrari

Implementarea unei functii simple (XOR cu 3 intrari):

-trei ploturi din stanga sunt configurate ca intrari,
-un bloc logic este utilizat pentru a crea un XOR cu 3 intrari,
-un plot din dreapta este configurat ca iesire,
-liniile de interconectare programabile asigura propagarea semnalelor in sistem.
Fig.3. Circuitul echivalent, corespunzator implementarii din figura 2.
 simple componente macroblocuri

Fig.4. FPGA ca simple componente sau ca macroblocuri de sisteme pe un singur “chip”

In cazul sistemelor de comunicatie, blocurile logice configurabile pot fi

modificate dinamic in vederea adaptarii la protocoale de comunicatii mai
performante;
2. Circuite logice configurabile.
Blocurile logice programabile trebuie sa fie capabile sa implementeze toate
functiile logice de baza:
NOT, AND,…..,XOR, XNOR etc…

Pentru implementarea acestora se pot folosi mai mule abordari, de exemplu:

-multiplexoare, (1)

-tabele asociative (lookup tables) (2).

MULTIPLEXORUL – functii implementabile

Configuration
ABS F= 0YX ABS X.Y
000 0 000 0

A 0X1 X 001 0
0Y1 Y 010 0
F
0YX XY 011 1
B
X0Y XY X0Y ABS X.Y(NEG)
Y0X YX 000 0
Y1X X+ Y 001 0
10X X 100 1
S 10Y Y 101 0
111 1
2.1. Multiplexoare

Multiplexoarele cu doua intrari pot fi utilizate ca generatoare programabile de functii,

Alte functii ( XOR) necesita cel putin doua multiplexoare (Fig. 6):
-cu o iesire de tip buffer, un multiplexor cu doua intrari are minim 6 tranzistoare si 3
etaje, care introduc intarzieri: doua inversoare si un tranzistor de trecere.
-un MUX cu 4 intrari are 18 etaje, care introduc intarzieri, astfel implementarile cu
multiplexoare nu sunt eficiente.
2.2. Tabele asociative (Look Up Tables).

Tab.2. Tabela de adevar a portii XOR, cu 3 intari, pentru implementarea in forma de tabela
asociativa
0*0 =0 *0 = 0 0*0 =0 *1 = 1 0*0=0
0*1=1 * 0 = 1 0*1=1 *1 = 0 0*1=1
1*0=1* 0 = 1 1*0=1* 1 = 0 1*0=1
1*1=0 * 0 =0 1*1=0 * 1 =1 1*1=0
Fig. 7. Iesirea f genereaza functia logica Fout, in conformitate cu tabela asociativa stocata in
punctele de memorare Value[i].
Punctele de memorare.
Punctele de memorare sunt utilizate pentru stocarea valorilor logice ale functiei date in tabela de
adevar a acesteia.

Registru de deplasare formatdin bistabile de tip D, in care bistabilui i memoreaza informatia

logica Value[i]. Bistabilele D sunt inlantuite pentru a reduce numarul semnalelor de control la un
semnal de ceas ClockProg si la un semnal de date DataProg.
Se genereaza o serie de 8 fronturi cazatoare de catre semnalul ClockProg.

La fiecare front activ, registrul de deplasare

este alimentat cu o noua valoare prezentata
secvential la intrarea DataProg.

Mai intai trebuie sa fie introdusa Value[7] si ultima

Value[0].
Impulsul DataProg trebuie sa descrie tabela de
adevar in ordine inversa
2.3. Fuzibile si Antifuzibile
-Pentru a retine configurarea in absenta tensiunii de alimentare - memorii nonvolatile,
programabile o singura data - fuzibil.
-De regula, se utilizeaza ca fuzibil un contact intre doua straturi de metal, contact care va fi
distrus de la aplicarea unui curent de intensitate mare

Fig.11. Contacte bazate pe fuzibile.

Fig.12. Programarea fuzibilelor.
Antifuzibilul are starea normala “deschis”
O tensiune mare (cca 10V) aplicata intre straturile metal1 si metal2 distruge oxidul, asigurand un
traseu conductiv intre straturile de metal.
ONO (Oxid-Nitrura-Oxid), SiO2 asigura o cale rezistiva atunci cand este programata. Valoarea
tipica a rezistentei este de 500 Ohm.

Pentru programarea circuitelor FPGA, EEPROM si FRAM se folosesc alte tipuri de memorii
nonvolatile. Aceste memorii nu sunt alterate atunci cand nu sunt alimentate si pot fi reprogramate
de un numar mare de ori.
 Blocul Logic Programabil.

Iesirea LUT este conectata direct la iesirea blocului Fout.

Iesirea este aplicata si la intrarea registrului D, prin multiplexorul controlat de DataIn_Fout.
Reteaua DataOut poate transfera direct semnalul DataIn, ceea ce face ca celula sa fie transparenta.
Semnalaul DataOut poate, de asemenea, furniza semnalul nQ, in functie de starea multiplexorului controlat de
DataIn_nQ.
Se inlantuie semnalele DataIn_Fout si DataIn_nQ in structura unui registru de deplasare format din doua
bistabile suplimentare cu rolul de sincronizare
 2. Interconectarea blocurilor

strategia de interconectare a blocurilor logice

punctele de interconectare programabile

matricile de conectare programabile

Punctele de conectare programabile
Fig. 19. Structura interna a PIP si ilustrarea comportarii sale On/Off
Fig.20. Matrice de PIP-uri
Matrice de comutare.

Posibilităţi de interconectare a două linii

 Fig. 23. Porti de transmisie amplasate pe liniile de rutare in vederea construirii matricii.
Bistabilele D sunt inlantuite pentru utilizarea unei singure intrari DataIn si a unui semnal de ceas LoadClock,
care sunt suficiente pentru configurarea matricii
Tablouri de Blocuri.

Fig. 24. Blocuri configurabile, matrice de comutare, I/E configurabile si tablouri

de PIP-uri.
Exemplu de Sumator Complet.

Sumator complet
A B C SUM CARRY RESULT
0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 1 0 1
0 1 1 0 1 2
1 0 0 1 0 1
1 0 1 0 1 2
1 1 0 0 1 2
1 1 1 1 1 3
Tab.3. Tabela de adevar a sumatorului complet.
 0

Fig. 25. Functiile SUM si CARRY care realizeaza un sumator complet in FPGA.
Fig. 26. Sumatorul complet implementat in doua blocuri configurabile
Specific hardware technologies such as field programmable gate
arrays (FPGAs) can also be considered as an appropriate solution in
order to boost the performance of controllers. These generic
components combine:
-low cost development,
-use of convenient software tools
-more and more significant integration density.
FPGA technology applications:

-wireless telecommunications
-image and signal processing
-medical equipment,
-robotics, automotive
-space and aircraft embedded control systems.

For these embedded applications, reduction of the power

consumption, thermal management and packaging, reliability,
and protection against solar radiation are of prime importance.
Industrial electrical control systems
-power converter control, (PWM) inverters,
power-factor correction, multilevel converters
- matrix converters, soft switching
- electrical machines control (induction machine
drives, switched reluctance machine (SRM)
drives, motion control
- multimachines systems, neural network (NN)
control of induction motors, fuzzy logic control
of power generators, and speed measurement.
1) Decrease of the cost for at least three reasons.
-The use of an architecture based only on the specific needs
of the algorithm to implement
-The application of highly advanced and specific
methodologies improving implementation time, also called
“time to market,”
- Expected development in VLSI design that will allow
integrating a full control system with its analog interface
in a single chip, also called System-on-a-Chip (SoC).
.
 2) Confidentiality, a specific architecture, integrating the
know-how of a company, is not easily duplicable.

3) Embedded systems with many constraints as in aircraft

applications, like limited power consumption, thermal
consideration, insensibility to el. and magnetic field
4) Improvement of control performance:
-execution time can be dramatically reduced by
designing dedicated parallel architectures
-an FPGA-based controller can be adapted in runtime
to the needs of the plant by dynamically reconfiguring it.
More recently, it has also been observed inside these architectures
the introduction of:
- dedicated blocks such as RAM, DSP accelerators
hardwired multipliers with corresponding accumulators,
high-speed clock management circuitry
serial transceivers,
- embedded hard processor cores such as
PowerPC or ARM
soft processor cores such as Nios or Microblaze
- integration of an analog to digital converter in the fusion
component

However, this SoC trend does not replace the former generic architecture,
but it can be seen as a complement to this original matrix.
The designer can take advantage of HDLs (Hardware description
Language) to build his own circuit by using the design “top-down
methodology”.

The corresponding design flow is partitioned into the following

four steps:
1) system level, where specifications of the circuit are
given;
2) behavior level that consists in the algorithmic
description of the circuit;
3) register transfer level (RTL), where the circuit is
described in term of its components;
4) physical level, where the circuit is physically described
by taking into account the target hardware characteristics.
specifications of
the circuit are
given;
algorithmic
description of the circuit

register transfer
level (RTL)
FPGA technology allows developing specific hardware
architectures within a flexible programmable environment.

This specific feature of the FPGAs gives designers a new degree

of freedom comparing to microprocessor implementations, since
the hardware architecture of the control system is not imposed
a priori.
In order to benefit from the advantages of the FPGAs and their
powerful CAD tools, the designer has to follow an efficient
design methodology. Such a methodology rests on three main
principles:
- the control algorithm refinement,
- the modularity,
-the best suitability between the algorithm to implement
and the chosen hardware architecture.
 Simplification of the -to avoid operators like multipliers
Computation -distributed arithmetic, that can make extensive
Algorithm use of LUTs
refinement
-reduce the number of operations to be
implemented

Search for Optimized

Fixed-Point Format

Design Methodology Based on Reuse Modules

Modularity
A3 Methodology Data Flow Graph (DFG)
Design of the A3 Optimized Architecture

Best suitability between algorithm to

implement hardware architecture
A. Algorithm Refinement
It is possible to implement floating-point arithmetic on FPGAs, but
the resources used are not optimized in this case because of FPGA sea-of-
logic-cells architectures

Therefore, in order to reduce cost, manufacturers require from end-

users to design controllers using fixed-point arithmetic. In this context, cost
efficient architectures must result from a balance between control
performances to respect and complexity of the hardware architecture to
minimize. This leads to formulate two work directions:
1) Simplification of the Computation:
S-mart solutions to avoid including greedy operators like multipliers.
Commonly used techniques of simplification, CORDIC, an acronym for
COordinate Rotation Digital Computer.

CORDIC is a very efficient algorithm, which is only based on

adders/subbtractors and shifters for computing a wide range of trigonometric,
hyperbolic, linear and logarithmic functions.

Another interesting family of algorithms is the distributed arithmetic,

that can make extensive use of LUTs, which makes it ideal in implementing
DSP functions in LUT-based FPGAs.

Finally, as explained thereafter, the designer can also take advantage in

remodeling the target algorithm in order to reduce the number of operations to
be implemented
2) Search for Optimized Fixed-Point Format
-A search for the best tradeoff (compromise) between the size of the
fixed-point format of each control variable and the respect of the control
specifications is needed.
-To this purpose, a methodology based L1 or l1 norms for
computing the appropriate number of bits to represent each quantity of a
controller (coefficients and variables) is recomended
B. Design Methodology Based on Reuse Modules
-For complex designs, modular conception is generally used to
reduce the design cycle.
-Based on hierarchy and concepts. Hierarchy is used to divide
a large or complex design into subparts called modules that are
more manageable.
A module can be defined as an element of a library, available to the designer,
which can be directly inferred (used) without having to design it.

Therefore, the reuse methodology consists in selecting, throughout the synthesis

process, elements of a library that are useful for the design in progress.

Fig. 4 presents two types of reuse IP module libraries that can be constituted,
one at behavioral level and the other one at RTL level.
C. A3 Methodology
To be efficient, the modular design approach must be
based on reliable (sure) modules. However, in many cases,
desired modules do not already exist, and they have to be built.
It is therefore crucial, when designing them, to be helped by an
efficient methodology that allows taking into account the
numerous constraints of such systems.

The goal of the A3 methodology, when applied to FPGAs, is

to find out an optimized hardware architecture for a given
application algorithm while satisfying time/area constraints.
A3 is based on graphmodels to exhibit both the potential
parallelism of the algorithm and the available parallelism of the
proposed architecture.

The (a, b, c) to (d, q) transformation case is treated in order to

illustrate the effectiveness of this methodology.
1) Data Flow Graph (DFG): Having finalized the algorithm
refinement procedure, the DFG of the algorithm is directly
derived from (3). The DFG establishes all the potential
parallelisms of the algorithm.

Each node represents an operation, and each edge represents a

dependence of data between two operations.
2) Design of the A3 Optimized Architecture:
The repetitive patterns of the DFG presented in Fig.
5 can then be advantageously factorized by using the A3
methodology in order to match the required hardware
constraints.

This leads to several data-path possibilities. Operations are

now replaced by operators.

In the case of the coordinate transformation algorithm, four

different ALU data paths can be derived from the A3
factorization process, as shown in Fig. 6.
Notice that, for simplicity reason, only the transformation
and computation parts of this algorithm have been treated
in this example. A3 methodology could be also applied with
success to sine function generation, also included in the
(a, b, c) to (d, q) transformation algorithm. Then, the different
data paths are compared taking into account their performance
in terms of latency, speed, and size area in order to get the
best tradeoff (compromise) between all these constraints.
 Xb

Xa A21 A22
A12 A11

* * * *

+- +-
Ann (theta)
Xq
Xd