L8-L9-Fixed Point Arithmetic MDFD

Lecture 8 and Lecture 9
Fixed Point Arithmetic

CSC208A-Computer Organisation and Architecture
B. Tech. 2016
Course Leaders
Chaitra S., Naveeta, Gp Capt N Rath VSM
1
Faculty of Engineering & Technology © Ramaiah University of Applied Sciences
Objectives
• At the end of these lectures, students will be able to
– Describe the process of performing basic mathematical
operations on signed and unsigned numbers
– Explain how these mathematical operations are

implemented using register/circuit diagrams
– Identify the need for fast adders and fast multipliers
– Distinguish between restoring division and non restoring

division
2
Contents
• Addition and Subtraction of Signed Numbers
– Full Adder
– Ripple Carry Adder
– N-bit Ripple Carry Adder
• Multiplication of Unsigned Numbers

– Array Multipliers
– Sequential Circuit Multipliers
• Multiplication of Signed Numbers

– Booth’s Algorithm
• Division of Unsigned Numbers

– Restoring Division
– Non Restoring Division
3
Contents
• Addition and Subtraction of Signed Numbers
– Full Adder
– Ripple Carry Adder
– N-bit Ripple Carry Adder
• Multiplication of Unsigned Numbers

– Array Multipliers
– Sequential Circuit Multipliers
• Multiplication of Signed Numbers

– Booth’s Algorithm
• Division of Unsigned Numbers

– Restoring Division
– Non Restoring Division
4
Addition and Subtraction of Signed Numbers
• Consider the addition of two binary numbers X and Y
5
• The generic expression to arrive at the sum and carry
for each bit is given by
6
• For example, the addition of the 4 bit unsigned
numbers, 7 and 6 is shown below
7
Half Adder
8
Half Adder
9
Half Adder (Continues…)
10
Half Adder (Continues…)
11
Half Adder (Continues…): CD4011
(QUAD 2 Input Nand Gate)
12
Full Adder
13
Full Adder: Truth Table
14
Full Adder: Another Implementation
• The logic expressions for sum and carry out can be implemented
with a 3 input XOR gate and an AND-OR circuit respectively
• This collective implementation is called a Full Adder
15
Ripple Carry Adder
• A cascaded connection of n full-adder blocks can be used
to add two n-bit numbers
• Since the carries must propagate, or ripple, through this

cascade, the configuration is called a ripple-carry adder
16
n Bit Ripple Carry Adder: k n bit FA
• The carry-in into the LSB position provides a
convenient means of adding 1 to a number
• The carry signals are also useful for interconnecting k

adders to form an adder capable of handling input
numbers that are kn bits long
17
Addition/Subtraction: Overflow
• Arithmetic overflow occurs when the signs of the two
operands are the same, but the sign of the result is
different
Overflow = xn−1yn−1sn−1 + xn−1yn−1s_n−1
• Overflow also occurs when the carry bits cn and cn-1

are different
Overflow = cn ⊕ cn-1
18
Addition/Subtraction: 2’s Compliment
• Recall that the difference between calculating X + Y and X – Y lies
in the two’s complement
X – Y = X + (2’s complement(Y))
Where,
2’s complement (Y) = 1’s Complement (Y) + 1
This implies that
X – Y = X + 1’s Complement (Y) + 1
• Implementation-wise, the difference between addition and

subtraction is whether there is a (1’s complement +1) component
or not
19
Addition/Subtraction: 2’s Compliment
• Recall that the difference between calculating X + Y and X – Y lies
in the two’s complement
X – Y = X + (2’s complement(Y))
Where,
2’s complement (Y) = 1’s Complement (Y) + 1
This implies that
X – Y = X + 1’s Complement (Y) + 1
• Implementation-wise, the difference between addition and

subtraction is whether there is a (1’s complement +1) component
or not
20
Addition/Subtraction Logic Unit
21
22
0/1
23
• This logic can be implemented in the ALU using an
Add/Sub input control line
• Add/Sub input control line is set to 0 for addition

– Y is applied unchanged to one of the adder inputs and Co is
set to 0
• Add/Sub input control line is set to 1 for subtraction

– 1’s complement of Y is calculated using the XOR gates
– 2’s complement is achieved by setting Co to 1
24
n bit Ripple Carry Adder- Timing Issues
25
4 bit Ripple Carry Adder- Gate Delays
27
4 bit Ripple Carry Adder- Gate Delays
28
n bit Ripple Carry Adder- Gate Delays
• Consider a 4 bit Adder
x0 y0 x0 y0 x0 y0 x0 y0
FA FA FA FA c0
c4 c3 c2 c1
s3 s2 s1 s0
• s0 available after 1 gate delays, c1 available after 2 gate delays

29
n bit Ripple Carry Adder-Timing Issues
• In general, for an n-bit adder
– sn-1 is available after 2n-1 gate delays
– cn is available after 2n gate delays
– Overflow indicator is available after 2n+2 gate delays
• Two approaches can be taken to reduce delay in

adders
– The first approach is to use the fastest possible electronic
technology
– The second approach is to use a logic gate network called a
carry-look ahead network
30
A 4 Bit Carry Look Ahead Adder
31
A 4 Bit Carry Look Ahead Adder
• A = An An-1 …. A1 A0
• B = Bn Bn-1 …. B1 B0
• Cn = Gn-1+Gn-2.Pn+Gn-3.Pn-2+ … +C0.P0.P1. … .Pn-1
• Gn = An.Bn
• Pn = An XOR Bn
• C1 = G0+C0.P0
• C2 = G1+ G0.P1+C0.P0.P1 32
Multiplication of Unsigned Numbers
33
Multiplication of Unsigned Numbers
• The product of two, unsigned, n-digit numbers can be accommodated in
2n digits
• If the multiplier bit is 1, the multiplicand is entered in the appropriate

shifted position and if the multiplier bit is 0, then 0s are entered
• The product is computed at the End one bit at a time by adding the bit
columns from right to left and propagating carry values between columns
34
Array Multipliers
• Instead of adding the parallel products at the end, we
could add them at each stage
• Rules to implement multiplication are:

– If the ith bit of the multiplier is 1, shift the multiplicand (left) and
add the shifted multiplicand to the current value of the partial
product
– Hand over the partial product (Sum) to the next stage
– Value of the partial product (Sum) at the start stage is 0
35
Array Multipliers: Processing of 1 bit of m & q
Multiplicand
Multiplier
36
Multiplicand
Multiplier
mj AND qj (= mj MULT qj)
37
Multiplicand
Multiplier
FA Gets Three Inputs

and gives out Two O/Ps
38
Multiplicand
Multiplier
FA Gets Three Inputs

and gives out Two O/Ps
39
Array Multipliers
• Multiplicand is shifted by displacing it through an array
of adders
40
Array Multipliers
of adders
Carry Out
41
Array Multipliers
of adders
Carry Out
42
Disadvantages of Array Multipliers
• Extremely inefficient
• Have a high gate count for multiplying numbers of

practical size such as 32-bit or 64-bit numbers
• Perform only unsigned integer product
• Gate efficiency can be improved by using a mixture of

combinatorial array and sequential techniques
43
Sequential Circuit Multiplier
• Recall the rule for generating partial products:
– If the ith bit of the multiplier is 1, add the appropriately shifted
multiplicand to the current partial product
• Multiplicand has been shifted left when added to the

partial product
• However, adding a left-shifted multiplicand to an unshifted

partial product is equivalent to adding an unshifted
multiplicand to a right-shifted partial product
44
Exercise: Seq Mult (13X11)
M
1 1 0 1
Q
1 0 1 1
45
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
46
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1 Step 1
MX1
47
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1 Add
48
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1 Add
0 1 1 0 1 1 0 1 1
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M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1 Shift 1 bit right
0 1 1 0 1 1 0 1 1
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M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1 Shift 1 bit right
0 0 1 1 0 1 1 0 1 1
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M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
52
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
Step 2
0 1 1 0 1 1 1 0 1
MX1
53
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
0 1 1 0 1 1 1 0 1 Add
54
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
0 1 1 0 1 1 1 0 1 Add
1 0 0 1 1 1 1 0 1
55
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
0 1 1 0 1 1 1 0 1 Add
1 0 0 1 1 1 1 0 1
What Next ?
56
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
0 1 1 0 1 1 1 0 1 Add
1 0 0 1 1 1 1 0 1
Shift Right
57
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
0 1 1 0 1 1 1 0 1 Add
1 0 0 1 1 1 1 0 1
What Next ?
58
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
0 1 1 0 1 1 1 0 1 Add
1 0 0 1 1 1 1 0 1
Add…
59
M
1 1 0 1
C A Q
0 0 0 0 0 1 0 1 1
0 1 1 0 1 1 0 1 1
0 0 1 1 0 1 1 0 1
0 1 1 0 1 1 1 0 1 Add
1 0 0 1 1 1 1 0 1
Add…
60
Panoramic View: Sequential Cct Multiplier Proc
• 1101 (Dec 13) X 1011 (Dec 11) using Sequential Cct
Multiplier (SCM)
61
62
Depending on q0 = 1 or q0 = 0
63
Sequential Circuit Multiplier-Steps
• If the LSB q0=1:
– Add the multiplicand to A
– Store carry-out in flip-flop C
• Else if q0 = 0
– Do not add
• Shift the contents of register A and Q to the right, and discard q0
• The Add/Noadd signal causes the multiplexer MUX to select 0

when qi = 0, or to select the multiplicand M when qi = 1, to be
added to PPi to generate PP(i + 1)
64
Try This…
• Show the steps involved in multiplying the numbers
1001 and 1100 using a sequential step multiplier
65
Multiplication of Signed Numbers
• Consider the case of a positive multiplier and a negative
multiplicand
• When we add a -ve multiplicand to a partial product, we must

extend the sign-bit value of the multiplicand to the left as far as
the product will extend (2n)
66
Andrew Donald Booth’s Algorithm: 1950 London
• The Booth algorithm generates a 2n-bit product and treats
both positive and negative (2’s complement) n-bit
operands uniformly
• It (the algo) converts strings of 1's in the multiplier

– to a high-order +1 And a
– low-order –1 @ ends of the string
• When a string runs through the MSB, there is no high-

order +1, and the net effect is interpretation as a negative
of the appropriate value
67
Booth’s Algorithm
• Let m and r be the multiplicand and multiplier, respectively; and let x
and y represent the number of bits in m and r
Step 1: Determine the values of A and S, and the initial value of P. All of
these numbers should have a length equal to (x + y + 1)
– A : Fill the most significant (leftmost) bits with the value of m. Fill the
remaining (y + 1) bits with zeros
– S: Fill the most significant bits with the value of (−m) in two's complement
notation. Fill the remaining (y + 1) bits with zeros
– P: Fill the most significant x bits with zeros. To the right of this, append the
value of r. Fill the least significant (rightmost) bit with a zero.
68
Booth’s Algorithm: Action based on 2 LSBs of P (Step 2)
• Step 2: If the two least significant (rightmost) bits of P
are:
– 01, find the value of P + A. Ignore any overflow
– 10, find the value of P + S. Ignore any overflow
– 00 & 01 do nothing. Use P directly in the next step
• Step 3: Right Shift P by 1 Bit
• Step 4: Repeat steps 2 and 3 until they have been
done y times
• Step 5: Drop the LSB from P to get mXr

69
Example
• Find 3 × (−4), with m = 3 and r = −4, and x = 4 and y = 4:
Solution:
m = 0011, -m = 1101, r = 1100
A = 0011 0000 0
S = 1101 0000 0
P = 0000 1100 0
Perform the loop four times
70
Example
• P = 0000 1100 0(The last two bits are 00)
– P = 0000 0110 0 (Arithmetic right shift)
• P = 0000 0110 0 (The last two bits are 00)


– P = 1101 0011 0 (P = P + S)

Dropping the last bit,

Product = 1111 0100
71
Try This…
• Multiply each of the following pairs of signed 2’s-
complement numbers using the Booth algorithm
• In each case, assume that A is the multiplicand and B is

the multiplier
I. A = 010111 and B = 110110

II. A = 110011 and B = 101100
III. A = 001111 and B = 001111
72
Division of Unsigned Numbers
• Consider the following example for longhand
integer division
– We try to divide 2 by 13 – Does not work
– We try to divide 27 by 13 – Works with quotient 2 and

remainder 1
– We bring the 4 down and append it to the previous

remainder
– We try to divide 14 by 13 – Works. Append 1 to the

quotient and subtract 13 from 14 to get the final
remainder
73
Restoring Division
• The divisor is positioned appropriately with respect to the
dividend and performs a subtraction
• If the remainder is zero or positive, a quotient bit of 1 is

determined, the remainder is extended by another bit of
the dividend, the divisor is repositioned, and another
subtraction is performed
• If the remainder is negative, a quotient bit of 0 is

determined, the dividend is restored by adding back the
divisor, and the divisor is repositioned for another
subtraction
74
Circuit Arrangement for Restoring Division
75
Circuit Arrangement for Restoring Division
• An n-bit positive divisor is loaded into register M and an n-bit
positive dividend is loaded into register Q at the start of the
operation
• Register A is set to 0
• After the division is complete, the n-bit quotient is in register Q

and the remainder is in register A
• The required subtractions are facilitated by using 2’s-

complement arithmetic
• The extra bit position at the left end of both A and M

accommodates the sign bit during subtractions
76
Algorithm For Restoring Division
• Do the following steps n times:
– Shift A and Q left one bit position.
– Subtract M from A, and place the answer back in A
– If the sign of A is 1, set q0 to 0 and add M back to A (that is,

restore A)
– If the sign of A is 0 set q0 to 1
77
Example
• Given that dividend = 1000 and divisor = 11, show how
the answer is obtained using the restoring division
algorithm
78
Try This…
• Given that dividend = 1101 and divisor = 10, show how
the answer is obtained using the restoring division
algorithm
79
Non Restoring Division
• Consider the sequence of operations that takes place after the
subtraction operation in the preceding algorithm
• If A is positive, we shift left and subtract M, that is, we perform

2A-M
• If A is negative, we restore it by performing A+M, and then we

shift it left and subtract M
• This is equivalent to performing 2A+M
• The q0 bit is appropriately set to 0 or 1 after the correct

operation has been performed
80
Algorithm for Non-Restoring Division
Stage 1: Do the following two steps n times:
– If the sign of A is 0, shift A and Q left one bit position and
subtract M from A;
– Otherwise, shift A and Q left and add M to A.
– Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
Stage 2: If the sign of A is 1, add M to A
• Stage 2 is needed to leave the proper positive remainder

in A after the n cycles of Stage 1
81
Example-Non Restoring Division
82
Summary
• The logic expressions for sum and carry out can be implemented with a 3 input
XOR gate and an AND-OR circuit respectively
• Arithmetic overflow occurs when the signs of the two operands are the same,
but the sign of the result is different
• Gate efficiency can be improved by using a mixture of combinatorial array

techniques and sequential techniques requiring less combinational logic
• Adding a left-shifted multiplicand to an unshifted partial product is equivalent

to adding an unshifted multiplicand to a right-shifted partial product
• The Booth algorithm generates a 2n-bit product and treats both positive and
negative 2’s complement n-bit operands uniformly
83

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Lecture 8 and Lecture 9

Fixed Point Arithmetic

– Explain how these mathematical operations are

– Identify the need for fast adders and fast multipliers

– Distinguish between restoring division and non restoring

• Multiplication of Unsigned Numbers

• Multiplication of Signed Numbers

• Division of Unsigned Numbers

• Multiplication of Unsigned Numbers

• Multiplication of Signed Numbers

• Division of Unsigned Numbers

• This collective implementation is called a Full Adder

• Since the carries must propagate, or ripple, through this

• The carry signals are also useful for interconnecting k

• Overflow also occurs when the carry bits cn and cn-1

This implies that

X – Y = X + 1’s Complement (Y) + 1

• Implementation-wise, the difference between addition and

This implies that

X – Y = X + 1’s Complement (Y) + 1

• Implementation-wise, the difference between addition and

• Add/Sub input control line is set to 0 for addition

• Add/Sub input control line is set to 1 for subtraction

• s1 available after 3 gate delays, c2 available after 4 gate delays

• s2 available after 5 gate delays, c3 available after 6 gate delays

• s3 available after 7 gate delays, c4 available after 8 gate delays

• Two approaches can be taken to reduce delay in

• Cn = Gn-1+Gn-2.Pn+Gn-3.Pn-2+ … +C0.P0.P1. … .Pn-1

• If the multiplier bit is 1, the multiplicand is entered in the appropriate

• Rules to implement multiplication are:

– Hand over the partial product (Sum) to the next stage

– Value of the partial product (Sum) at the start stage is 0

mj AND qj (= mj MULT qj)

mj AND qj (= mj MULT qj)

FA Gets Three Inputs

mj AND qj (= mj MULT qj)

FA Gets Three Inputs

• Have a high gate count for multiplying numbers of

• Perform only unsigned integer product

• Gate efficiency can be improved by using a mixture of

• Multiplicand has been shifted left when added to the

• However, adding a left-shifted multiplicand to an unshifted

0 1 1 0 1 1 0 1 1 Shift 1 bit right

0 1 1 0 1 1 0 1 1 Shift 1 bit right

• Shift the contents of register A and Q to the right, and discard q0

• The Add/Noadd signal causes the multiplexer MUX to select 0

• When we add a -ve multiplicand to a partial product, we must

• It (the algo) converts strings of 1's in the multiplier

• When a string runs through the MSB, there is no high-

• Step 5: Drop the LSB from P to get mXr

Perform the loop four times

• P = 0000 0110 0 (The last two bits are 00)

• P = 0000 0011 0 (The last two bits are 10)

• P = 1110 1001 1 (The last two bits are 11)

Dropping the last bit,

• In each case, assume that A is the multiplicand and B is

I. A = 010111 and B = 110110

– We try to divide 2 by 13 – Does not work

– We try to divide 27 by 13 – Works with quotient 2 and

– We bring the 4 down and append it to the previous

– We try to divide 14 by 13 – Works. Append 1 to the

• If the remainder is zero or positive, a quotient bit of 1 is

• If the remainder is negative, a quotient bit of 0 is