AGENDA

• What is DFT? Why it is required?

• Importance of Testing.

• What is Testability?

• Manufacturing defects.

• DFT Architecture.

• Manufacturing Defects.
 What is DFT?

• DFT refers to the hardware design styles, or added hardware that reduces test generation complexity.

• Motivation :- Test generation complexity increases exponentially with the size of design.

• Basically DFT enables the manufacturing test.

• It is a structural technique, which facilitates a design to become testable after production.

 WHY DFT
• To increase Productivity:

Shorter time -to-market :- DFT ensures the release of the chip into the market within the

specified time without any defects.

Reduced cost:- Testing and debugging the chip with low cost.

Reduces the test complexity, test time and tester requirements.

• To Improve Quality:

Detect the manufacturing defects early in the design stage.

Reduced Defects per million(DPM)

Improved quality of test : - Means improving test coverage to the required percentage.
 Importance of Testing
• Since times design size is decreasing.

• Defects are unavoidable.

• Testing is required to guarantee fault- free chips.

• Product quality depends on following parameters

Test cost

Test quality

Test time

• Hence DFT came into existence to deliver the cost effective, defect-free quality designs.
 What is Testability?

• The ability to put the design into a known initial state, and then control and observe internal signal
values.

• Two basic properties determines the testability of a node are :-

Controllability : The ability to set node to a specific value.

Observability : The ability to observe a node’s value.

 DFT Architecture

• Scan Insertion

• Compression

• MBIST

• ATPG

• JTAG Boundary scan

• Simulation
 Scan Insertion
• Scan Insertion goal is to increase the controllability and observability of a circuit.

• The most common is scan design technique which modifies the internal sequential circuit.

• Scan circuit facilitates test generation and can reduce external tester usage.

• Internal scan is the modification of design’s circuitry to increase its testability with
two states mainly - shift & capture depending on SCAN_ENABLE.

• Achieving this goal involves replacing sequential elements with scan cells and stitching them together into
scan registers or scan chains.
 Compression
2. Decompress and load 3. Captured responses
scan chains
• Compression of scan test data by controlling a large
number of internal scan chains using small number of
scan channels.

• The main theme is to reduce test data and test

volume.

• There is no impact on functional design.

• Adds minimal test logic.

• Easily fits into the design flow. 1. Compressed stimuli from 4. Compact, unload and
ATE to decompressor compare responses
 ATPG
• ATPG : Automatic test pattern generation .
• Targets manufacturing faults.
• Different from functional testing
• Functional testing focuses on Functionality of the design.
• Manufacturing tests focuses on detecting Manufacturing defects and Reliability of the
device.

 The Goal of ATPG is to create a set of patterns that achieves a given test coverage.
 ATPG consists of two main steps :
1) Generating patterns and
2) Performing fault simulation to determine which faults are the patterns detected.
Methods of Pattern Generation
• The two most typical methods of pattern generation are

Random
Deterministic

Test Types
• Functional Test
• Stuck –At
Stuck-at 0
Stuck-at 1
• At-speed Test
Transition Delay
Path Delay
• IDDQ Test
• Memory Test
 Simulations

• Resolve mismatches using simulation data.

• Check the mismatches on scan cells inputs as well as primary output pins.

• Debugging serial & parallel simulation Mismatches.

• Through analysis of simulation data.

• Tracing back the source of mismatched data.