Buffering

 To Drive large load, special buffers capable of delivering current at high

speed are essential.

 Load may be on-chip such as the clock distribution network or off-chip

such as the pad drivers.

An effective way to minimize large

capacitive load is to implement a Buffer

Tapered Buffer that is a chain of Large Load

inverters with a gradual increase in

driving capability

• The Objective: Given a load capacitance, CL design a scaled (tapered)

chain of N inverters such that the delay time between the logic gate
and the load capacitance node is minimized
The task is to determine: number of stages (N) and the tapering factor (S)

CONCORDIA 1
VLSI DESIGN LAB
 OUTPUT Pad and Driver

CONCORDIA 2
VLSI DESIGN LAB
 CLOCK DRIVER

CONCORDIA 3
VLSI DESIGN LAB
 Buffering

S = scaling or tapering factor

CL = SN+1 Cg ………………

All inverters have identical delay of

CONCORDIA to = delay of the first stage (load =Cd+Cg) 4
VLSI DESIGN LAB
 Buffering

If the diffusion capacitance Cd is neglected, then S = e = 2.7

S
4

0 1 2 3
CONCORDIA
Cd/Cg 5
VLSI DESIGN LAB
 Layout of a standard inverter
Diffusion

Polysilicon Wp
PMOS

Metal
Vin
Vo

Wn
L
NMOS

VSS
CONCORDIA 6
VLSI DESIGN LAB
 Layout of Large Device

•Drain-Source Area
•Delay of Gate

CONCORDIA 7
VLSI DESIGN LAB
 Layout of a Buffer
D(rain)
S
Multiple
Contacts
D

S(ource)

G(ate)

(a) small transistors in parallel (b) circular transistors

CONCORDIA 8
VLSI DESIGN LAB Prentice Hall/Rabaey
 Large Transistor Layout

Increase # of
Contacts

CONCORDIA 9
VLSI DESIGN LAB
 Output Drivers

Standard CMOS Driver

Open Drain/Source Driver: Single Transistors

Tri-state Driver

Bi-directional Circuit

CONCORDIA 10
VLSI DESIGN LAB
 Output Drivers
Bonding Pad GND

100 mm
Out

Out

VDD
In GND
CONCORDIA 11
VLSI DESIGN LAB Prentice Hall/Rabaey
 Tri-state Driver

 Tri-state or High impedance VDD

 Used to drive internal or external busses
 Two inputs:
Data In and Enable
 Various signal assertions En
Out
 Two types: In
C2MOS
CMOS with Control Logic En

C2MOS
CONCORDIA 12
VLSI DESIGN LAB
 Tri-state Driver

VDD
Control logic could be
modified to obtain En
Inversion/non-inversion
Active low/high Enable
Out PAD
For large load, pre-drivers
are required En
In

CONCORDIA 13
VLSI DESIGN LAB
 Latch-up on CMOS
Inherent in bulk CMOS processes are parasitic bipolar transistors forming
p+/n /p /n+ path between VDD and VSS

The four layer path is equivalent to SCR which when triggered can cause self
sustaining latch-up between power supplies resulting in total or local
destruction.
VDD VDD
VSS

n+ p+ p+ n+ n+ p+ Rs Drain of
NMOS
T1 Rw T2 T1
T2
P-well Drain of
Rs
PMOS
Rw

n-substrate
Vss

CONCORDIA 14
VLSI DESIGN LAB
 Latch-up: Analysis
 If VA>VDD+0.6, T1 will be turned ON
 Ic1 causes a voltage drop across Rw
 If V(Rw) > 0.6V V, T2 will be turned ON, VDD
this forces Ic2 to be supplied by VDD through
n+ substrate contact, then the bulk to p-well. IE1
 Increase in voltage across Rs causes and in
increase in Ic1, hence sustaining SCR action. Rs
IB1 VA
T1
 The same action will take place when: IC1
IC1
VB< -0.6V T2
IB2
 Hence to prevent latch-up, limit the output VB

voltage Rw
IE1
-0.6< Vout < VDD+0.6V

VSS

CONCORDIA 15
VLSI DESIGN LAB
 Latch-up: Trigger

Factors which trigger latch-up

 transmission line reflections or ringing

 voltage drop on the VDD bus
 “hot plug in” of unpowered circuit board
 electrostatic discharge
 sudden transient on power and ground busses
 leakage current across the junction
 radiation: x-ray, cosmic

CONCORDIA 16
VLSI DESIGN LAB
 Latch-up: Prevention
1. Layout techniques:
Incorporate collectors for latch-up current:
Create diffused n and p guard rings that surround active devices
These collectors can sink the current but are incapable of
sustaining the latch-up mechanism once the cause is removed

guard ring

n+ n+ n+
n+

p+ p+ p+
p+
GND
CONCORDIA 17
VLSI DESIGN LAB
 Input protection

Electrostatic discharge can take place through transfer of charges from the
human body to the device.
Human body can carry up to 8000V.
Discharge can happen within hundreds of nanoseconds.
Critical field for SiO2 is about 7X106 V/cm.
For 0.5u CMOS process the gate oxide can withstand around 8V
Some protection technique is required with minimum impact on
performance 1M 1.5K

Vesd DUT
100pF

Human Body model

CONCORDIA 18
VLSI DESIGN LAB
 Input PAD

CONCORDIA 19
VLSI DESIGN LAB
 Protection Circuitry Principles

Punch Through Avalanche

CONCORDIA 20
VLSI DESIGN LAB
 Vd
d

Input Circu
Pad it

Vs
s

CONCORDIA 21
VLSI DESIGN LAB
 ESD Structures
Basic technique is to include series resistance and two clamping
diodes.
The resistance R is to limit the current and to slow down the high
voltage transitions.
R could be polysilicon or diffusion resistance
Diffusion resistance could be part of the diode structure
Typical values of R: 500 to 1k
VDD

R
PAD

CONCORDIA 22
VLSI DESIGN LAB
 Protection Circuitry
Based on gate
modulated junction
breakdown

CONCORDIA 23
VLSI DESIGN LAB
 Protection Circuitry

CONCORDIA 24
VLSI DESIGN LAB
 Layout of ESD Structure

This structure
uses transistors as PAD
clamping diodes

n+
p+
Guard Ring Guard Ring
p+

p+ n+
n+

CONCORDIA 25
VLSI DESIGN LAB
 Layout of ESD Structure
VDD

PAD

n+
p+
Guard Ring Guard Ring
p+

p+ n+
n+

GND
CONCORDIA 26
VLSI DESIGN LAB
 Guard Rings VDD

for critical
Transistors

Vin

Diffusion

n+ N

Contact
Vss
Polysilico
Diffusion P+
n
CONCORDIA 27
VLSI DESIGN LAB Metal
 VDD

CONCORDIA 28
VLSI DESIGN LAB
 Structure of a P+ Diode
VDD

N+ Guard

M1
N Sub

P+

Input
OUTPUT
CONCORDIA 29
VLSI DESIGN LAB
 Another ESD Structure

VDD

R1 R2
PAD

Thick FOX
MOS Transistor

CONCORDIA 30
VLSI DESIGN LAB
 Bi-direct PAD
VDD

Pre-drivers

IN ESD Protection Input Buffer

Control
Logic PAD
EN

CONCORDIA 31
VLSI DESIGN LAB
 D2 D3 1X 4X

PAD R
D1 D4
D1 D2 D3 D4
R SiO2 Metal– to CCT

N+ P+ N+
N-Well @ VDD

P substrate connected to Gnd

CONCORDIA
VLSI DESIGN LAB
 2D vs. 2.5D vs. 3D ICs 101 By:
Clive Maxfield 4/8/2012 12:08 PM EDT

Birds-eye view of circuit board with

Birds-eye view of circuit board a System-on-Chip (SoC) device
with individually packaged chips

Birds-eye view of circuit board with Birds-eye view of circuit board with
a System-in-Package (SiP) device
CONCORDIA a System-in-Package (SiP) device 33
VLSI DESIGN LAB
 3D Structures
2D vs. 2.5D vs. 3D ICs 101 By:
Clive Maxfield 4/8/2012 12:08 PM EDT

Connecting dice using wires running down

A simple form of 3D IC/SiP the sides 3D stack

A more complex “True 3D IC/SiP

A simple “True 3D IC/SiP”

CONCORDIA 34
VLSI DESIGN LAB
 Thank you !

CONCORDIA 35
VLSI DESIGN LAB