EDA Introduction: Professor: Sci.D., Prof. Vazgen Melikyan

EDA Introduction
Professor: Sci.D., Prof. Vazgen

Melikyan
Synopsys University Courseware

Copyright © 2017 Synopsys, Inc. All rights reserved.
EDA Introduction
Lecture - 2
1 Developed By: Vazgen Melikyan
Course Overview
 Introduction
 1 lecture
 IC Design Data Formats and Tools
 4 lectures
 Electronic Design Methodology
 4 lectures
 IC Synthesis
 2 lectures
 Databases for EDA
 3 lectures
 IC Design Approaches and Flows
 3 lectures
 EDA Tools
 3 lectures
 Overview of Synopsys EDA Tools
 3 lectures

EDA Introduction
Lecture - 2
IC Design Data Formats and
Tools

EDA Introduction
Lecture - 2
Components of Electronic Design
Technical Methodical
Organizational Mathematical
EDA
Information Linguistic
Software

EDA Introduction
Lecture - 2
Technical Support
 Requirements for technical support:

 Execution of all necessary design stages when software is
available
 Performed when EDA, computers and other technical systems with
sufficient performance and memory capacity are available
 Interaction between designers and computers, support for
interactive mode
 Runs when user-friendly interface in EDA
 Interaction between team members working on a common project
 Performed by the union of hardware, EDA in area network

EDA Introduction
Lecture - 2
Technical Support Structure
Node A Node B
… Тransmission media
…
 Nodes (station data) are the workplaces of designers,

called automatic workplace (AW); they can also be
mainframes, separate peripheral and measuring devices.
EDA Introduction
Lecture - 2
Types of Data Networks
 Two methods of sharing transmission data lines

 TDM - Time Division Method
 A time slice is allocated to each channel
 FDM - Frequency Division Method
 A frequency band is allocated to the channel
 In the EDA of not large design organizations, with one or tens of computers,
which are placed at short distances from one another (for example, in one
or more adjacent rooms), the network that brings the computers together is
called local.
 LAN (Local Area Network) - a communication line to which all the nodes in
the network are connected.
 In large-scale design organizations the network includes tens or hundreds
or more computers belonging to various design and management units and
placed in the premises of one or more buildings. Such a network is called
corporate.
EDA Introduction
Lecture - 2
Topologies of Local Area Network
…
…
…
…
A - bus b - ring c - star

EDA Introduction
Lecture - 2
The Structure of Corporate Network
Corporative servers Access to Subscriber

network WAN line
Backbone
network
Basic network
Local server
Access
servers
LAN
LAN
LAN
LAN -Local Area Network WAN — Wide Area Network

EDA Introduction
Lecture - 2
Electronic Design Methodology
 Core of EDA:
 Theory of processes occurring in the design
 Methods of analysis and synthesis of systems and their components
 Methods of analysis and synthesis of schemes and structures
 Mathematical models
 Mathematical methods and algorithms for solving equation systems
 Electronic Design Methodology also includes special

algorithmic programming languages, terminology,
standards and other data.

EDA Introduction
Lecture - 2
Electronic Design Methodology (2)
 A group of mathematical methods, models and

algorithms of design, necessary for design automation.
Mathematical methods
Design algorithms
Mathematical models

EDA Introduction
Lecture - 2
Formal Design Languages
 A group of formal design languages (including transition from one language

into another, coding and density methods), necessary for design
automation.
Design language 1
Formalization rules
Natural language
Design language 2
Coding and density

methods
Design language n

EDA Introduction
Lecture - 2
Formal Design Languages (2)
EDA languages
Input Development Output Information
Languages Languages
Hardware compliant with compliant with
description High level the existing databases and
languages algorithmic standards and its control
(HDL): VHDL; languages: C; manufacturing system,
Verilog, etc. C++, etc. equipment: GDS, OpenAccess,
OASIS, etc. Milkyway, etc.

EDA Introduction
Lecture - 2
HDLs
 Hardware Description Languages

 Widely used in logic design
 Verilog and VHDL
 Description of hardware using code

 Documenting logic functions
 Simulating logic before building
 Synthesizing code into gates and layout
 Requires a library of standard cells
EDA Introduction
Lecture - 2
Verilog Example
module fulladder(input a, b, c,
output s, cout);
a bc
sum s1(a, b, c, s);

carry c1(a, b, c, cout); a b
endmodule c sum
cout carry
s
fulladder
module carry(input a, b, c,
s
output cout) cout
assign cout = (a&b) | (a&c) |

(b&c);
endmodule

EDA Introduction
Lecture - 2
Gate-Level Netlist
module carry(input a,b,c,

output cout) g1
a x
b
wire x, y, z; g2 g4
a y
c cout
and g1(x, a, b);
g3
and g2(y, a, c); b z
c
and g3(z, b, c);
or g4(cout, x, y,z);
endmodule

EDA Introduction
Lecture - 2
Transistor-Level Netlist
module carry(input a, b, c,
output cout)
wire i1, i2, i3, i4, cn;
tranif1 n1(i1, 0, a);

a p1 b p2 b p4
tranif1 n2(i1, 0, b); i4
tranif1 n3(cn, i1, c); c p3 i3 a p5 p6
tranif1 n4(i2, 0, b); cn
cout
tranif1 n5(cn, i2, a);
tranif0 p1(i3, 1, a);
c n3 i1 a n5 n6
tranif0 p2(i3, 1, b);
i2
a n1 b n2 b n4
tranif0 p3(cn, i3, c);
tranif0 p4(i4, 1, b);
tranif0 p5(cn, i4, a);
tranif1 n6(cout, 0, cn);
tranif0 p6(cout, 1, cn);
endmodule

EDA Introduction
Lecture - 2
Spice Netlist
.SUBCKT CARRY A B C COUT VDD GND

MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P
MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P
AS=0.5P
MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P
MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P
MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P
MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P
MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P
MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P
MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P a p1 bp2 b p4
MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P i4
CI1 I1 GND 2FF c p3 i3 a p5 p6
CI3 I3 GND 3FF cn
CA A GND 4FF
cout
CB B GND 4FF c n3 i1 a n5 n6
CC C GND 2FF i2
CCN CN GND 4FF
a n1 b n2 b n4
CCOUT COUT GND 2FF
.ENDS

EDA Introduction
Lecture - 2
File Formats
File Expansion Description
SDF Standard Delay Format Industry standard format
giving pin to pin delays
PDEF Physical Design Exchange Format Industry standard format for
physical cluster and
placement information
(initiated by Synopsys)
DEF Design Exchange Format Format for physical data
exchange (mostly used for
storing physical constraints,
floor plan , etc.)
SPEF Standard Parasitic Exchange Format Industry standard format
LEF Library Exchange Format Standard format used for
PLEF Parametric LEF exchanging layout data
between programs
 SDF files can be read by Design Compiler – contains both gate delays and interconnect delays.
 SDF can also be generated by Design Compiler. VHDL/Verilog simulators can also use SDF.
EDA Introduction
Lecture - 2
SDF Example
DELAYFILE
(SDFVERSION “OVI 2.1”)
(DESIGN “COUNTER4”) Header Information
(DATE “Wed Jul 27 08:18:43 2000”)
(VENDOR “class”)
(PROGRAM “Acme EDA Co.”)
(VERSION “2000.11”)
(DIVIDER /)
(VOLTAGE 5.00:5.00:5.00)
(PROCESS “typical”)
(TEMPERATURE 25.00:25.00:25.00)
(TIMESCALE 1ns)
(CELL
(CELLTYPE “IVA”)
Min:Typical:Max
(INSTANCE U41)
(DELAY
(ABSOLUTE
(IOPATH A Z (0.350:0.350:0.350) (0.340:0.340:0.340))
)))
Rising delays Falling delays

Delay from input pin to output pin
EDA Introduction
Lecture - 2
SDF Example (2)
(CELL
(CELTYPE “FD1”) Setup/Hold constraints
(INSTANCE REG_BLK1/FO)
(DELAY
(ABSOLUTE
(IOPATH CP Q (3.199:3.199:3.199) (2.126:2.126:2.126))
))
(TIMINGCHECK
(SETUP D CP (0.800:0.800:0.800))
(HOLD D CP (0.400:0.400:0.400))
))
(CELL
(CELLTYPE “counter”) Interconnect delays
(INSTANCE)
(DELAY(ABSOLUTE
(INTERCONNECT mt_reg_18/QN U31/I (.006:.006:.006)(.005:.005:.005))
(INTERCONNECT U8/ZN U95/A2 (.235:.235:.235) (.250:.250:.250))
(INTERCONNECT U8/ZN U97/A2 (.229:.229:.229) (.244:.244:.244))
))))

EDA Introduction
Lecture - 2
PDEF – Physical Design Exchange
Format
 Exchanges clustering information between
front-end tools (logic synthesis - Design
Compiler) and back-end tools (physical layout
– IC Compiler)
 ‘Clustering’ means that the layout tool needs to place
a group of cells (a cluster) close together because
they are related
 This minimizes routing delays between these cells

EDA Introduction
22
Lecture - 2
Developed By: Vazgen Melikyan
22
PDEF (2)
Logic Hierarchy
TOP Information in logic
synthesis tool
U1 U2
U1 U5 U1 U4
U2 U7 U2 U5 Leaf Cells
U3 U8 U3 U6
U4
Phisical Hierarchy
Top
TOP cluster
U2/U1 U1/U1
Clust1 U2/U2 U1/U2 Clust3
U1/U8 U1/U3
U1/U4 U2/U3 U2/U6
U1/U5 U2/U4
U1/U7 U2/U5 Clust2 Placement by floorplanner

EDA Introduction
Lecture - 2
PDEF Example
(CLUSTERFILE
(PDEFVERSION “2.0”)
(DESIGN “top”) 6,1966”)
(VENDOR “Synopsys,Inc.”)
(PROGRAM “Design Compiler”)
(VERSION “v3.5”) Cluster definition
(DIVIDER /)
(CLUSTER
(NAME “TOP_CLUSTER”)
(X_BOUNDS 0.0 50.0)
(Y_BOUNDS 0.0 50.0)
(CLUSTER
(NAME “Clust1”)
(X_BOUNDS 0.0 20.0)
(Y_BOUNDS 0.0 20.0)
(CELL (NAME U2/U1) (LOC 10.0 10.0))
(CELL (NAME U1/U8) (LOC 6.3 7.0))
)

EDA Introduction
Lecture - 2
SPEF - Standard Parasitic Exchange
Format
 Exchanges parasitics between layout tools and delay calculators -
delay calculators use parasitics to produce SDF files.
*R_NET rgb_reg_data_outE_23 0.56

/* *R_NET net_name total_cap */
*DRIVER RGB_REGISTERS/reg_out5_reg_23/Q
/* *DRIVER pin_name */
*CELL DFFX1
/* *CELL cell_name */
*C2_R1_C1 0.028 0.076 0.028
/* *C2_R1_C1 C2_value R1_value C1_value*/
*LOADS
*RC SHIFT/U23/A 0.002/**RC load_pin load_value*/
*RC SHIFT/U14/A 0.001/**RC load_pin load_value*/

EDA Introduction
Lecture - 2
LEF - Library Exchange Format
[ VERSION number
NAMESCASESENSITIVE statement
NOWIREEXTENSIONATP IN statement
 LEF files describe physical
BUSBITCHARS statement
DIVIDERCHAR statement ]
information for layout libraries
[ UNITS statement ]
[ PROPERTYDEF INITIONS statement ]
{ LAYER (Nonrouting) statement
used by external place/route tools.
| LAYER (Routing) statement } . . .
{ VIA statement }
{ VIARULE statement
 Header contains information for
| VIARULE GENERATE statement }. . .
[ NONDEFAULTRULE statement ] technology (layers, spacing, etc).
[ UNIVERSALNOISEMARGIN statement ]
[ EDGERATETHRESHOLD1 statement]
[ EDGERATETHRESHOLD2 statement]
[ EDGERATETHRESCALEFACTOR statement ]
 Macro statements define each cell
[ NOISETABLE table]
[ CORRECTIONTABLE table] (pins and obstructions – timing
[ SPACING statement ]
[ MINFEATURE statement ]
[ DIELECTRIC statement ]
information needed for timing
[ IRDROP statement ]
{ SITE statement } . . . driven layout).
[ ARRAY statement ] . . .
{ MACRO macroName
Macro data
{ PIN statement } . . .
{ OBS statement } . . .
[ TIMING statement ]
END macroName} . . .

EDA Introduction
Lecture - 2
DEF- Design Exchange Format
VERSION statement
NAMESCASENSITIVE statement
BUSBITCHARS statement
 DEF files contain final placed/routed
DIVIDERCHAR statement
DESIGN statement
design.
[ TECHNOLOGY statement ]
[ ARRAY statement ]
[ FLOORPLAN statement ]  Produced by IC Compiler after
[ UNITS statement]
[ HISTORY statement ] . . .
placement/routing, can be imported
[ PROPERTYDEFINITIONS section ]
[ DIEAREA statement ] back
[ ROW statement ] . . .
[ TRACKS statement ] . . .
[ GCELLGRID statement ] . . .
[ DEFAULTCAP section ]
 Contains physical information for
[ CANPLACE statement ] . . .
[ CANNOTOCCUPY statement ] . . . routes, pin placement, cell placement.
[ VIAS statement ]
[ REGIONS statement ]
COMPONENTS section
[ PINS section ]
[ PINPROPERTIES section ]
[SPECIALNETS section ]
NETS section
[ IOTIMINGS section ]
[ SCANCHAINS section]
[ CONSTRAINTS section ]
[ GROUPS section ]
[ BEGINEXT section ]
END DESIGN statement

EDA Introduction
Lecture - 2
EDA Software
 An integrity of software, necessary for design automation and

presented as required.
 Software consists of:
 Systems software – controls software that occurs in design process
 Application software – obtains design solutions.
 Requirements to software
 Efficiency of design algorithms software (small machine time and memory
saving)
 Information consistency of different tools
 Consistency with DBCS
 Modular structure

EDA Introduction
Lecture - 2
System Software
 Consists of two parts:

 External
 Operational system, anticipated for program processing and ordering;
I/O planning and organization; distribution of machine resources and
data processing (Windows; Linux, etc.). Not an EDA object.
 Internal
 Anticipated for the organization of joint operation of EDA internal
software. It is invariant to the designed object and must be protected
from the user. Typical consistent parts of systems software of internal
part is the interactive dialog system; DBCS; information-search
system; graphical processing system; textual and graphical
information formation system; generalized calculations’ performing
system.
EDA Introduction
Lecture - 2
Application Software
 Application software (AS) represents a group of application software packages, used

in different phases of design for the solution of definite problems with corresponding
design solutions.
Generalized structure of IC EDA application software
IC EDA AS Design phases

Design actions
Circuit design AS Physical design Technological

Logic design AS
AS design AS
Structural Construction of Analysis of Parametrical Statistical

mathematical mathematical
synthesis optimization analysis
models models
Design Flows
EDA Introduction
Lecture - 2

EDA Introduction: Professor: Sci.D., Prof. Vazgen Melikyan

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Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 Requirements for technical support:

Synopsys University Courseware

 Nodes (station data) are the workplaces of designers,

 Two methods of sharing transmission data lines

A - bus b - ring c - star

Synopsys University Courseware

Corporative servers Access to Subscriber

LAN -Local Area Network WAN — Wide Area Network

 Electronic Design Methodology also includes special

Synopsys University Courseware

 A group of mathematical methods, models and

Synopsys University Courseware

 A group of formal design languages (including transition from one language

Coding and density

Synopsys University Courseware

Input Development Output Information

Synopsys University Courseware

 Hardware Description Languages

 Description of hardware using code

sum s1(a, b, c, s);

assign cout = (a&b) | (a&c) |

Synopsys University Courseware

module carry(input a,b,c,

Synopsys University Courseware

wire i1, i2, i3, i4, cn;

tranif1 n1(i1, 0, a);

Synopsys University Courseware

.SUBCKT CARRY A B C COUT VDD GND

Synopsys University Courseware

Rising delays Falling delays

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

*R_NET rgb_reg_data_outE_23 0.56

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 An integrity of software, necessary for design automation and

Synopsys University Courseware

 Consists of two parts:

 Application software (AS) represents a group of application software packages, used

Generalized structure of IC EDA application software

IC EDA AS Design phases

Circuit design AS Physical design Technological

Structural Construction of Analysis of Parametrical Statistical

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