What is µP?

• “An integrated circuit containing … a central

processing unit (CPU) and a means to access
external memory” -- (Ball 2000)
 Memory
• Memory types
– RAM
– ROM, PROM
– EPROM, EEPROM, Flash
• RAM Memory Cell
inactive read write
0 1

0 x 1 x x 1 xy y
 Bus
• Collection of signal lines -- uni(bi)directional
• Operation represented using timing diagrams
• Clocked vs Asynchronous separate data and address buses
 System Bus Control Signals
• Multiple users?
– arbitration
– sender/reciever id
• Multiplexed?
– data ready
– clock
• Block Transfer
– busy
PCI Bus -- Read
 CPU Architecture
VonNeumann Harvard
– code can be modified – data access does not
(accidentally) slow code access
– instruction and data
widths unrelated

Data CPU
Code
Data
CPU
Code Data Code
Data
 CPU Internals

ALU: Registers:
manipulates Storage
data in response for data
to signals from
the control unit

Bus: Control Unit:

Transports data issues control
between ALU path signals
and registers (micro-operations)
to other parts of
CPU
 CPU Architecture
Accumulator Stack Register

w=1; Push 1 Ra=1;

w=w+2; Push 2 Rb=2;
Add Ra=Ra+Rb;

2 0 1 1 1
0 1 3 1 1 3 0 0 2 3
Instruction vs. Micro-operation

Write
 Add Instruction - Fetch
Address Pnemonic Value
1101 1100 load 1 00 0001 10 0101
0001 1101 add 5 10 0101
1110 jmp 1100 ……….

1101
2 1110 1

1
PC
CU
IR
3 3
00 0001
10 0101
 Add Instruction - Indirect
(Decode)

1 ALU operation
Control
0 add signals

IR 0 bit 3
1 bit 2
0 bit 1 0101
1 bit 0

CU
 Add Instruction - Execute
1

0110 0001
add
2 ALU 3
1 3

CU

1 1
0101
Status flags
 RISC vs. CISC
• Single-cycle instruction
execution
– Simple, fixed instruction
format
– few instructions and
addressing modes
– Hardwired micro-operations
• Memory Access
– Load/Store design
– High-performance memory
(registers/cache).
• Predictable Speed/Performance
• Multi-cycle instruction
execution
– Variable size instruction format
– Micro-programmed instruction
set
• Smaller program size (# of
instructions)
• Memory Access
– Multiple addressing modes
• Optimization Complexity
 Pipelining
• Assumptions:
– stages all have same duration
– no branching
– consecutive instructions are independent

Fetch1 Indirect1 Execute1 Write1 Fetch2 Indirect2 Execute2 Write2

Fetch1 Indirect1 Execute1 Write1

Fetch2 Indirect2 Execute2 Write2
Fetch3 Indirect3 Execute3 Write3
Fetch4 Indirect4 Execute4 Write4
Fetch5 Indirect5 Execute5 Write5
 Architecture vs. Organisation
– Bit Widths – Control signals
– Instruction set – Micro-operation set
• CPU components • external interface
– bus operations – access times
– parallel/replicated – RAM: static vs. dynamic
functions? • physical layout
– Pipelining
– manufacturing process
– RISC/CISC
– logic family
– track length
– power/heat considerations
 Machine Instructions
Data transfer
Move register register
Store register memory
Load memory register
Exchange register register
Swap lo-nibble hi-nibble
Clear 00000000 register
Set 11111111 register
Push register stack
Pop stack register
 Machine Instructions
Arithmetic/Logical
increment, decrement, not
absolute, negate, register register
two’s-complement

add, subtract, multiply, divide

and, or, exclusive-or
register
OP register
register
 Machine Instructions:Bit--Logical
x
Bit-set, Bit-clear ···

Bit-test ··· == x?

Bit-compare ··· x == y ?
···

Shift Rotate
 Machine Instructions
Control transfer/Special purpose
• Program flow • Special:
– skip [PC]=[PC]+1 – input/output
– branch [PC]=? – data conversion
– call push [PC]; [PC]=?
– system operation
– return pop [PC]
• Compound
• Processing pause – conditional branch
– nop 1 cycle delay IF BIT-TST BRANCH
– sleep wait for event – return with value
– wait ? cycle delay LOAD VALUE
RETURN
Machine Instruction Examples
Add • Arithmetic
Load • Data Transfer
Branch • Control Transfer

Address Mnemonic Value

1100 load 1 00 0001
1101 add 5 10 0101
1110 jmp 12 01 1110

Op-code Operand
2 bits 4 bits
Addressing Modes

Displacement Variants
Relative
Base Register
Indexing
Post-Indexing
Pre-Indexing
 How Many Operands?
0-operand
1-operand 2-operand
PUSH 5 3-operand
PUSH 6 LOAD 5 LOAD R1,5 LOAD R2, 5
ADD ADD 6 ADD R1, 6 ADD R1, R1, R2

Stack Accumulator Register

Variable length instructions,
Operand Specified
Addressing Modes
 System Reset / Program Launch
Start

Operating System
0000 Branch 0100

0100 Load 5
0101 Add 2
0110 …...

1110 End

Halt
 Development Software
Tool Chain
IDE

Editor

Compiler

Linker Simulator

Download Live
Program

In-circuit
Debugger