ARCHITECTURAL

FEATURES AND
BLOCK DIAGRAM OF
ARM7 TDMI
Features of ARM7 TDMI

■ It is a 32-bit microcontroller
■ 32-bit address bus so it can access 4GB size of memory
■ 32-bit data bus and ALU
So it can complete 32-bit instructions in 1 cycle. That’s 4 times
faster than 8051.
■ TDMI- Thumb Instruction, Debugger, Multiplier, ICE
ARM7, a rigid performance-based
microcontroller
■ Aligned and misaligned data
– Aligned data: 16-bit data starts at even address
– Misaligned data: 16-bit data starts at odd address
32-bit data is stored in 4 consecutive locations
Addresses:
3 2 1 0 0000
7 6 5 4 0100
B A 9 8 1000
F E D C 1100
■ ARM does not allow misaligned data, hence it is called rigid.
■ All data should be stored starting with an address that is a multiple of 4 (i.e. last 2
bits are 00).
■ Aligned 32-bit data requires only 1-cycle for transfer, hence it is performance-
oriented.
■ ARM7 follows Von Neumann model of memory
■ That is, one common 4GB memory unit stores both programs and data.

4 GB MEMORY:

PROGRAM

DATA
ARM7- Advanced RISC processor

CISC- Complex Instruction Set Computer (8086)

(single instructions can execute several low-level operations)
In contrast to
RISC- Reduced Instruction Set Computer (ARM7)
(has a small set of simple and general instructions)
■ ARM7 can be called an advanced RISC processor as it has fewer cycles per
instruction
3 Stage instruction pipeline
■ The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions
to the processor.
■ The instruction pipeline is as shown:

• During normal operation, while one

instruction is being executed, its
successor is being decoded, and a
third instruction is being fetched
from memory.

• The program counter points to the

instruction being fetched rather
than to the instruction being
executed.
• A load/store architecture, where data-processing
operations only operate on register contents, not directly on
memory contents.
• A large uniform register file. Out of 37 registers(32 bits), 16
are available at a time(R0 to R15). Rest are banked
registers.
• 3 Data Formats : 8-bit (bytes), 16-bit (halfwords), 32-bit
(words).
• 7 Operating Modes
• 7 Interrupts / Exceptions
• 7 Addressing Modes
THE THUMB CONCEPT
■ The Thumb instruction set consists of 16-bit instructions that act as a compact
shorthand for a subset of the 32-bit instructions of the standard ARM. Every Thumb
instruction could instead be executed via the equivalent 32-bit ARM instruction. However,
not all ARM instructions are available in the Thumb subset; for example, there's no way
to access status or coprocessor registers. Also, some functions that can be
accomplished in a single ARM instruction can only be simulated with a sequence of
Thumb instructions.
■ At this point, you may ask why have two instruction sets in the same CPU? But really the
ARM contains only one instruction set: the 32-bit set. When it's operating in the Thumb
state, the processor simply expands the smaller shorthand instructions fetched from
memory into their 32-bit equivalents.
■ The difference between two equivalent instructions lies in how the instructions are
fetched and interpreted prior to execution, not in how they function. Since the
expansion from 16-bit to 32-bit instruction is accomplished via dedicated hardware
within the chip, it doesn't slow execution even a bit. But the narrower 16-bit
instructions do offer memory advantages.
■ The Thumb instruction set provides most of the functionality required in a typical
application. Arithmetic and logical operations, load/store data movements, and
conditional and unconditional branches are supported. Based upon the available
instruction set, any code written in C could be executed successfully in Thumb state.
However, device drivers and exception handlers must often be written at least partly
in ARM state.
ARM7 TDMI processor Block Diagram
• Embedded ICE-RT Logic:
1. The EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM7TDMI core.
2. The EmbeddedICE-RT logic is programmed serially using the ARM7TDMI processor TAP
controller.
3. The EmbeddedICE-RT logic comprises:
• two real-time watchpoint units
• three independent registers:
• debug control register
• debug status register
• abort status register.
• Debug Communications Channel (DCC).
The debug control register and the debug status register provide overall control of
EmbeddedICE-RT operation. The abort status register is used when monitor mode is selected.

• Scan Chains:
These enable serial access to the core logic and to EmbeddedICE Logic for programming purposes.
Each scan chain cell is fairly simple and consists of a serial register and a multiplexor. The scan
cells perform two basic functions:
• CAPTURE
• SHIFT
All the control signals for the scan cells are generated internally by the TAP controller.
TAP controller instructions to select one of the following basic modes of operation of the
scan chains:
• INTEST mode
• EXTEST mode
• SYSTEM mode

Scan chain 0
Scan chain 0 is intended primarily for inter-device testing, EXTEST, and testing the core,
INTEST.
Scan chain 1
The primary use for scan chain 1 is for debugging, although it can be used for EXTEST
on the data bus.
Scan chain 2
Enables the EmbeddedICE-RT macrocell registers to be accessed.
• D[31:0], DOUT[31:0], and DIN[31:0]:
1. The ARM7TDMI processor provides both unidirectional data buses, DIN[31:0],
DOUT[31:0], and a bidirectional data bus, D[31:0]. The configuration input BUSEN is
used to select which is active.
2. Bus splitter latch is used to separate these buses.
3. When the bidirectional data bus is being used then BUSEN must be LOW.
4. Figure shows the arrangement of the data buses and bus-splitter logic.
• Tap Controller:
The TAP controller is a state machine that determines the state of the ARM7TDMI-S,
which controls the flow of data bits to the Instruction Register (IR) and the Data
Registers (DR).
SCREG[3:0] number of scan chain currently selected
IR[3:0] TAP controller instruction register
TAPSM[3:0] TAP controller state machine
TCK1 test clock phase 1
TCK2 test clock phase 2
nTRST Selects the system mode
TCK is not necessary to reset the device
ARM7 TDMI Main Processor Logic
ALU
■ 32 bit data bus carrying both instructions and data
■ Two 32 bit inputs: One from the register file and other from the shifter
■ Output modifies the status register flag, V-bit goes to the V flag and Cout goes
to the C flag
■ Most significant bit is the S flag
■ Output of ALU is NORed to obtain the Z flag.
Booth multiplier
■ 32-bit inputs, all inputs from the register file
■ output: 32 least significant bits of the product
■ The multiplication starts whenever the start input goes active. The output fin
goes high when finishing
Barrel Shifter
■ The barrel shifter has a 32-bit input to be shifted. This input is coming from
the register file or it could be immediate data. The shifter has other control
inputs coming from instruction register
■ Shift field in the instruction controls the operation of the barrel shifter. This
field indicates the type of shift to be performed (logical left or right,
arithmetic right or rotate right).
■ The amount by which the register should be shifted is
contained in an immediate field in the instruction or it
could be the lower 6 bits of a register in the register file
REGISTERS
■ The ARM7TDMI has a total of 37 registers:
■ 31 general-purpose 32-bit registers
■ 6 status registers.
■ These registers are not all accessible at the same time. The processor state and
operating mode determine which registers are available to the programmer.

■ In ARM state, 16 general registers and one or two status registers are accessible at any
one time. In privileged modes, mode-specific banked registers become available. The
ARM-state register set contains 16 directly-accessible registers, r0 to r15.
■ A further register, the CPSR, contains condition code flags and the current mode bits.
■ Registers r0 to r13 are general-purpose registers used to hold either data or address
values.
■ By convention, r13 is used as the Stack Pointer (SP).
■ Registers r14 and r15 have the following special functions:
 Link register: Register r14 is used as the subroutine Link Register (LR). Register r14
receives a copy of r15 when a Branch with Link (BL) instruction is executed. At all
other times you can treat r14 as a general-purpose register. The corresponding
banked registers r14_svc, r14_irq, r14_fiq, r14_abt and r14_und are similarly used
to hold the return values of r15 when interrupts and exceptions arise, or when BL
instructions are executed within interrupt or exception routines.
 Program counter: Register r15 holds the PC. In ARM state, bits [1:0] of r15 are
undefined and must be ignored. Bits [31:2] contain the PC. In Thumb state, bit [0]
is undefined and must be ignored. Bits [31:1] contain the PC.
■ The Thumb state register set is a subset of the ARM state set. The programmer has
direct access to:
– eight general registers, r0–r7
– the PC
– a Stack Pointer (SP)
– a Link Register (LR)
– the CPSR.
■ There are banked SPs, LRs, and SPSRs for each privileged mode.
 PROCESSOR MODES

■ There are 7 operating modes out of which first six are privileged modes and the last
is non privileged mode.
1) Abort mode (abt): The processor enters abort mode when there is failed attempt to
access memory.
2) FIQ (fiq): Designed to support a data transfer or channel process.
3) IRQ (irq): Used for general-purpose interrupt handling.
4) Supervisor (svc): Protected mode for the operating system.
5) System (sys): A privileged user mode for the operating system that allows full read-
write access to the CPSR.
6) Undefined (und): Entered when an undefined instruction is executed.
7) User (usr): The normal ARM program execution state and used for programs and
applications.
 BANKED REGISTERS

■ Out of 32 registers ,20 registers are hidden from a program at different

times. These registers are called banked registers.
■ They are denoted by underline character post fixed the mode mnemonic or
_mode. e.g. r13_abt, r13_abt and spsr_abt .
■ When the T bit is 1,then processor is in thumb state . To change states core
executes a specialized branch instruction and when T=0 the processor is in
arm state and executes Arm instructions.
1. V(overflow): Set if the result causes a signed overflow.
2. C(Carry): Is set when the result causes an unsigned carry
3. Z(Zero): This bit is set when the result after an arithmetic operation is zero
, frequently used to indicate equality.
4. N(Negative): This set when the bit 31 of the result is a binary 1.