Topic 5

Layout Design
 Integrated Circuit Layout
• Integrated circuit layout, also known IC layout, IC mask
layout, or mask design, is the representation of an
integrated circuit in terms of planar geometric shapes
which correspond to the patterns of metal, oxide, or
semiconductor layers that make up the components of
the integrated circuit.
 IC Layout
• When using a standard process
– where the interaction of the many chemical, thermal, and
photographic variables is known and carefully controlled
– the behavior of the final integrated circuit depends largely on the
positions and interconnections of the geometric shapes.
• Using a computer-aided layout tool,
– the layout engineer / layout technician
– places and connects all of the components that make up the chip
such that they meet certain criteria typically:
• performance, size, density, and manufacturability.
 IC Layout Verification
• The generated layout must pass a series of checks in a
process known as physical verification such as
– design rule checking (DRC),
– layout versus schematic (LVS),
– parasitic extraction,
– antenna rule checking, and
– electrical rule checking (ERC).
 IC Layout Verification
• When all verification is complete, the data is translated into an
industry-standard format, typically GDSII, and sent to a
semiconductor foundry.
• The process of sending this data to the foundry is called tapeout
because the data used to be shipped out on a magnetic tape.
• The foundry converts the data into another format and uses it to
generate the photomasks used in a photolithographic process of
semiconductor device fabrication.
• Modern IC layout is done with the aid of IC layout editor software,
mostly automatically using EDA tools, including place and route
tools or schematic-driven layout tools.
• The manual operation of choosing and positioning the geometric
shapes is informally known as "polygon pushing”
 Function of IC Layout
• IC Layout is a bridge between the IC designers and the
IC manufacturers
• IC Designers will have an IC which he/she designs
based on certain requirement.
• Once designed, the IC designer will verify the design.
• The design will then be sent to the manufacturer, who
will fabricate the IC based on the design.
• The design rule are the interface between the designer
and the process engineer
 Types of Layout
• There are 2 types
– Stick Diagram
– Real Layout
 Stick Diagram
• VLSI design aims to translate circuit concepts onto
silicon.
• Stick diagrams are a means of capturing topography and
layer information using simple diagrams.
• Stick diagrams convey layer information through color
codes.
• Acts as an interface between symbolic circuit and the
actual layout.
 Stick Diagram
• Does show all components / vias.
– It shows relative placement of components.
– Goes one step closer to the layout
– Helps plan the layout and routing
• Basically “A stick diagram is a cartoon of a layout”.
• Does not show
– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub boundaries.
– Any other low level details such as parasitic.
• Units are represented in the units lambda (λ)
 Real Layout
• Also known as Physical Layout
• Is the actual placement of component on the silicon
wafer
• The designer will translate schematic circuit to stick
diagram to real layout.
• The real layout is represented in the units micron (μm)
 Stick Diagram Color Code
• The common color code are
 Stick Diagram Layout Rules
• Rule 1.
– When two or more ‘sticks’ of the same type cross or touch each other that
represents electrical contact.

• Rule 2.
– When two or more ‘sticks’ of different type cross or touch each other there is no
electrical contact. (If electrical contact is needed we have to show the connection
explicitly)
 Stick Diagram Layout Rules
• Rule 3.
– When a poly crosses diffusion it represents a transistor.

• Rule 4.
– In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All
PMOS must lie on one side of the line and all NMOS will have to be on the other
side.
 Weinberger Technique
• Also called “Weingberger approach” [weinberger67]
• This method (a structured approach) was traditionally
used in the 1980s where the data wires are routed in
parallel to the supply rails and perpendicular to the
diffusion areas.
• This technique was most efficient for bit sliced
datapaths, because of the “over the cell wiring”.
 Standard Cell Technique
• A more efficient technique has been introduced called
the “standard-cell technique”
• Signals are now routed vertically and polysilicon can
serve for both Nmos and Pmos devices.
• This has given been the focus of using the “Euler
Approach”.
• The Euler path technique has been used in what is
called the “standard cell technique”
– which results in a dense layout for CMOS gates and
– one polysilicon strip that can serve as the input to both NMOS
and PMOS devices.
Inverter using Weinberger
Inverter using Weinberger
Inverter using Weinberger
Inverter using Weinberger
Inverter using Weinberger
Inverter using Standard Cell
Inverter using Standard Cell
Inverter using Standard Cell
Inverter using Standard Cell
Inverter using Standard Cell
Inverter using Standard Cell
Inverter using Standard Cell
Euler Path Method
Euler Path Method
 Euler Path Method
Method: Stick diagrams are constructed in two steps.
1. The first step is to construct a logic graph of the schematic.
a) Identify each transistor by a unique name of its gate signal
(A, B, C, D, E).
b) Identify each connection to the transistor by a unique name
(1,2,3,4).
Euler Path Method
 Euler Path Method
2. The second step is to construct one Euler path for both the Pull
up network (PUN) and Pull down network (PDN).
A) Euler paths are defined by a path the traverses each node in the
path, such that each edge is visited only once.
B) The path is defined by the order of each transistor name.
i) If the path traverses transistor A then B then C. Then the path name is {A, B,
C}
C) The Euler path of the Pull up network must be the same as the
path of the Pull down network.
D) Euler paths are not necessarily unique.
F) It may be necessary to redefine the function to find a Euler path.
i) F = E + (CD) + (AB) = (AB) +E + (CD)
Euler Path Method
 Euler Path Method
3) Once the Euler path is found, it is time to layout the stick
diagram.
A) Trace two green lines horizontally to represent the NMOS and
PMOS devices.
 Euler Path Method
B) Trace the number of inputs (5 in this example) vertically across
each green strip. These represent the gate contacts to the devices
that are made of Poly (red).
 Euler Path Method
C) Surround the NMOS device in a yellow box to represent the
surrounding Pwell material.
 Euler Path Method
D) Surround the PMOS device in a green box to represent the
surrounding Nwell material.
 Euler Path Method
E) Trace a blue line horizontally, above and below the PMOS and
NMOS lines to represent the Metal 1 of VDD and VSS.
 Euler Path Method
F) Label each Poly line with the Euler path label, in order from left
to right.
 Euler Path Method
G) Place the connection labels upon the NMOS and PMOS
devices.
i) Connection 1 is the node that lies between the PMOS transistors A, B and E.
The Euler path defines the transistor ordering of {A, B, E, D, C} therefore,
transistor B is physically located beside transistor E. Place the connection label
1 between the transistors B and E. Later, we will route a Metal 1 connection
from the drain of transistor A to the connection label of 1.
 Euler Path Method
ii) Connection 2 is the node that connects the PMOS transistors of E, D, and C.
Since the Euler path places transistors E and D next to each other, place the
connection label between these two. Later, we will route a Metal 1 strip from the
source of C to connection label 2.
 Euler Path Method
iii) Connection label 3 lies between the NMOS transistors of A and B.
 Euler Path Method
iv) Connection label 4 lies between the NMOS transistors of D and C.
 Euler Path Method
H) Place the VDD, VSS and all output names upon the NMOS and
PMOS devices. The OUTPUT signal;
a) This signal is connected to the PUN device between transistors D and C.
b) The signal is connected to the PDN at the node that the three transistors of
A, E and D share. The Euler graph connects transistors E and D together so an
output connection will be located there. Transistor A has one remaining contact
that is unused, so the output label is placed at that position.
 Euler Path Method
ii) VDD is located upon the PMOS device at the node shared between
transistors A and B.
 Euler Path Method
iii) VSS is located upon the NMOS device at a node that is shared between
transistors B, E and C.
a) The Euler path places transistors B and E together so place a VSS label
between the transistors there.
b) Transistor C has one remaining contact that is unused. Place a VSS label
there.
 Euler Path Method
I) Place a blue line on the diagram to represent the output metal
one material. Note: this line may have to be moved around
depending on how the diagram connections will lay out.
 Euler Path Method
4) Now its time to interconnect the device. You will probably have to
experiment to find the best routing.
A) Connect the output
 Euler Path Method
B) Connect the VDD and the VSS
 Euler Path Method
C) Complete the interconnects
i) Unused node at transistor A to Node 1
ii) Unused node at transistor C to Node 2
 Euler Path Method
5) A word of advise
A) Notice that Poly and Metal 1 can overlap.
B) Avoid routing signals that are side by side for long lengths. This
adds capacitance to the device.
C) Avoid all interconnect overlap if possible. This adds capacitance
to the device.
D) Strive for simplicity. This will later provide the smallest and
fastest devices.
E) You can use Poly, Metal 2, and even Active to interconnect your
device.
i) Poly and especially Active adds resistance to you device.
ii) Avoid using Metal 2 if possible. Metal 2 is another layer to your device that
you will probably need in the next hierarchy up.
 Examples Of Stick Diagram
• Sketch the stick diagram for a 4 input NAND
4 input NAND Stick Diagram
• Convert the PMOS and NMOS from
vertical to horizontal.
4 input NAND Stick Diagram

• The schematic of a 4 input NAND Gate

4 input NAND Stick Diagram

• Flip PMOS B and D

4 input NAND Stick Diagram

• Draw metal wires for

– Vcc
– Gnd
– Output, F
4 input NAND Stick Diagram

• Place active areas

– Yellow for PMOS
– Green for NMOS
4 input NAND Stick Diagram

• Draw 4 Poly across the active areas for input A, B, C and D

4 input NAND Stick Diagram

• Draw contact where metal meet active

• Stick Diagram for 4 input NAND Gate Complete.
4 Input NOR Stick Diagram
4 Input NOR Stick Diagram
 Exercise
• Sketch the stick diagram for
– 3 input AND Gate
– 3 input OR Gate
– F = (A+B).CD
–
 Design Rule
• Design rules specify geometric constraints on the
layout artwork.
• Provide a communication channel between the IC
designer and the fabrication process engineer.
• Objective:
– To obtain a circuit with optimum yield.
– To minimize the area of the circuit.
– To provide long term reliability of the circuit.
• Design rules represent the best compromise between
performance and yield:
– More conservative rules increase yield.
– More aggressive rules increase performance.
• Design rules represent a tolerance that ensures high
probability of correct fabrication - rather than a hard
boundary between correct and incorrect fabrication.
 MOSIS SCMOS Design Rule
• MOSIS stands for Metal Oxide Semiconductor Implementation
Service and SCMOS stands for Scalable Complementary Metal
Oxide Semiconductor
• Founded in 1981 is the oldest IC foundry service.
• Designed to scale across a wide range of technologies.
• Designed to support multiple vendors.
• Designed for educational use.
• Ergonomic, fairly conservative.
• For more information go to
• https://www.mosis.com/files/scmos/scmos.pdf
 General Design Rules
• Line size and spacing:
• metal1: Minimum width=3λ, Minimum Spacing=3 λ
• metal2: Minimum width=3 λ, Minimum Spacing=4 λ
• poly: Minimum width= 2 λ, Minimum Spacing=2 λ
• ndiff/pdiff: Minimum width= 3 λ, Minimum Spacing=3 λ,
Minimum ndiff/pdiff seperation=10 λ
• wells: Minimum width=10 λ,
min distance well edge to source/drain=5 λ
 General Design Rules
• Transistors:
• Min width=3λ
• Min length=2λ
• Min poly overhang=2λ

• Contacts (Vias)
• Cut size: exactly 2λ X 2 λ
• Cut separation: minimum 2 λ
• Overlap: min 1 λ in all directions
• Contacts cannot stack (i.e., metal2/metal1/poly)
 General Design Rules
• Other rules
• cut to poly must be 3 λ from other poly
• cut to diff must be 3 λ from other diff
• metal2/metal1 contact cannot be directly over poly
• negative features must be at least 2 λ in size
General Design Rules
 Measurement Units
• There are two measurement units
– Lambda
– Micron
• Lambda are unit that are scalable whereas Micron is the
absolute dimensions.
• Every distance in layout rules is specified by lambda
• Given a process, lambda is set to a specific value.
– Process technology is defined using minimum line width. 0.25um technology
means minimum line width is 0.25um. Lambda=minimum line width/2.
– For a 0.25um process, lambda=0.125um
• In practice, scaling is often not linear.
• Industry usually uses micron rule and lambda rule is used only
for prediction/estimation of the impact of technology scaling to a
design.
 Measurement Units
• There are two measurement units
– Lambda
– Micron
• Lambda are unit that are scalable whereas Micron is the
absolute dimensions.
• Every distance in layout rules is specified by lambda
• Given a process, lambda is set to a specific value.
– Process technology is defined using minimum line width. 0.25um technology
means minimum line width is 0.25um. Lambda=minimum line width/2.
– For a 0.25um process, lambda=0.125um
• In practice, scaling is often not linear.
• Industry usually uses micron rule and lambda rule is used only
for prediction/estimation of the impact of technology scaling to a
design.
 Basic Geometry Rules
• There are three most basic design rules.
1) A width rule specifies the minimum width of any shape in the
design.
2) A spacing / separation rule specifies the minimum distance
between two adjacent objects.
3) A two layer rule / overlap rule specifies a relationship that must
exist between two layers.
Basic Geometry Rules
Layout of a CMOS inverter
Layout of a CMOS NAND
Layout of a CMOS NOR
 Exercise
• Draw the Layout using L-Edit for
– 3 input AND Gate
– 3 input OR Gate
– F = (A+B).CD
–
Design Rule Check Output
Layout Versus Schematic (LVS)
• The Layout Versus Schematic (LVS) is the class of electronic
design automation (EDA) verification software that determines
whether a particular integrated circuit layout corresponds to the
original schematic or circuit diagram of the design.
• A successful Design rule check (DRC) ensures that the layout
conforms to the rules designed/required for faultless fabrication.
• However, it does not guarantee if it really represents the circuit
you desire to fabricate - this is where an LVS check is used.
• LVS checking software recognizes the drawn shapes of the
layout that represent the electrical components of the circuit, as
well as the connections between them.
• This netlist is compared by the "LVS" software against a similar
schematic or circuit diagram's netlist.
Layout Versus Schematic (LVS)
• LVS Checking involves following three steps:
• 1) Extraction:
– The software program takes a database file containing all the layers drawn
to represent the circuit during layout.
– It then runs the database through many area based logic operations to
determine the semiconductor components represented in the drawing by
their layers of construction.
– Area based logical operations use polygon areas as inputs and generate
output polygon areas from these operations.
– These operations are used to define the device recognition layers, the
terminals of these devices, the wiring conductors and via structures, and
the locations of pins (also known as hierarchical connection points).
– The layers that form devices can have various measurements performed to
and these measurements can be attached to these devices.
– Layers that represent "good" wiring (conductors) are usually made of and
called metals.
– Vertical connections between these layers are often called vias.
Layout Versus Schematic (LVS)
• LVS Checking involves following three steps:
• 2) Reduction:
– During reduction the software combines the extracted components into
series and parallel combinations if possible and generates a netlist
representation of the layout database.
– A similar reduction is performed on the "source" Schematic netlist.
• 3) Comparison:
– The extracted layout netlist is then compared to the netlist taken from the
circuit schematic.
– If the two netlists match, then the circuit passes the LVS check.
– At this point it is said to be "LVS clean." (Mathematically, the layout and
schematic netlists are compared by performing a Graph isomorphism
check to see if they are equivalent.)
Layout Versus Schematic (LVS)
• LVS Checking involves following three steps:
• 1) Extraction:
– The software program takes a database file containing all the layers drawn
to represent the circuit during layout.
– It then runs the database through many area based logic operations to
determine the semiconductor components represented in the drawing by
their layers of construction.
– Area based logical operations use polygon areas as inputs and generate
output polygon areas from these operations.
– These operations are used to define the device recognition layers, the
terminals of these devices, the wiring conductors and via structures, and
the locations of pins (also known as hierarchical connection points).
– The layers that form devices can have various measurements performed to
and these measurements can be attached to these devices.
– Layers that represent "good" wiring (conductors) are usually made of and
called metals.
– Vertical connections between these layers are often called vias.
• Reduction: During reduction the software combines the