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VLSI Design Methodology

Design Rules
Simulation Models and parameters
Silicon IC Design
Mask Layouts
Foundry Team
Integrated circuits (IC)

CAD Tool
Process Information Provider Software Tools

Relationship between a silicon foundry,

an IC design team and a CAD tool provider
Design Methodology
 Full Custom
Semi Custom
Standard Cell Based
Gate Array Based
Structured Gates

 Programmable

ASIC Design Methodologies
ASIC Design Methodology

Full-custom Standard-cell Gate-array FPGA based

design based design based design design

 This approach is  This approach is  This approach is  The design process

extremely slow, reasonable fast, fast and less is very fast and
expensive less expensive expensive cost effective

 It is only used to  Most ASICs are  ASIC performance  ASIC performance

design very high currently designed are relatively slow are slow
performance using this method
Full-custom IC
 Each circuit element carefully “handcrafted”

 Every transistor designed and laid out by hand

 Huge design effort

 High Design & NRE Costs / Low Unit Cost

 High Performance

 Typically used for high-volume and specific applications

Full-custom IC
 A full-custom IC includes some (possibly all) logic cells that are
customized and all mask layers that are customized.

 A microprocessor is an example of a full-custom IC—designers

spend many hours squeezing the most out of every last square
micron of microprocessor chip space by hand.

 It allows designers to include analog circuits, optimized memory


 Full-custom ICs are the most expensive to manufacture and to

design. The manufacturing lead time (the time it takes just to
make an IC—not including design time) is typically eight weeks
for a full-custom IC.
Full-custom IC
 In a full-custom ASIC an engineer designs some or all of
the logic cells, circuits, or layout specifically for one ASIC.

 This means the designer abandons the approach of using

pretested and precharacterized cells for all or part of that

 It makes sense to take this approach only if there are no

suitable existing cell libraries available that can be used for
the entire design.

 Fewer and fewer full-custom ICs are being designed

because of the problems with these special parts of the
ASIC. There is one growing member of this family, though,
the mixed analog/digital ASIC.
Semicustom ASICs
 Semicustom ASICs , in which all of the logic cells are predesigned
and some (possibly all) of the mask layers are customized. Using
predesigned cells from a cell library makes our lives as designers
much, much easier. There are two types of semicustom ASICs:

 Standard-cell–based ASICs & gate-array–based ASICs.

 Programmable ASICs ,in which all of the logic cells are

predesigned and none of the mask layers are customized. There
are two types of programmable ASICs: the programmable logic
device and, the newest member of the ASIC family, the field-
programmable gate array.
Semicustom ASICs
Standard-Cell–Based ASICs
 A cell-based ASIC ( CBIC —“sea-bick”)

 Standard cells – like Logic Gates, flip flops ,

multiplexers, full adder, decoder,

Possibly megacells, megafunctions, full-custom blocks, system-level

macros ( SLMs), fixed blocks,cores, or Functional Standard Blocks ( FSBs )

 All mask layers are customized—transistors and

Standard-Cell–Based ASICs

 Custom or flexible blocks

can be embedded

 One or more fixed blocks

 Manufacturing lead time is

about eight weeks.
 Consists of set of logic functions in the cell

 Able to accurately simulate and model

electrical characteristics of logic gates

 Export all the characterized information in an

standard format
Gate-Array–Based ASICs

A gate array masked gate array MGA or prediffused array uses


 There are three types:

 Channeled gate arrays

 Channelless gate arrays

 Structured gate arrays

Channeled Gate Array
 A channeled gate array
Only the interconnect is customized

The interconnect uses predefined

spaces between rows of base cells

Manufacturing lead time is between

two days and two weeks
Channeled Gate Array
 A “wall” of standard cells forms a flexible block
 Metal2 may be used in a feed through cell to cross
over cell rows that use metal1 for wiring
 Other wiring cells: spacer cells , row-end cells , and
power cells
Channelless Gate Array
A channelless gate array /
channel-free gate array / sea-
of-gates array, or SOG array)

 Only some (the top few) mask layers

are customized— the interconnect

 Manufacturing lead time is between

two days and two weeks.
Structured Gate Array
An embedded gate array Or structured
gate array (masterslice or master image)

• Only the interconnect is customized

• Custom blocks (the same for each
design) can be embedded

• Manufacturing lead time is between two

days and two weeks.
Programmable ASICs
 There are two types of programmable ASICs:
 Programmable logic devices (PLDs) and
 Field-programmable gate arrays (FPGAs).

PLDs started as small devices that could replace a handful of TTL parts,
and they have grown to look very much like their younger relations, the

 An IC foundry produces FPGAs with some connections missing. User

perform design entry and simulation. Next, special software creates a
string of bits describing the extra connections required to make your
design—the configuration file .

 The user then connect a computer to the chip and program the chip to
make the necessary connections according to the configuration file. There
is no customization of any mask level for an FPGA, allowing the FPGA to
be manufactured as a standard part in high volume.
Programmable Logic Devices

 No customized mask layers or logic cells

 Fast design turn around

 A single large block of programmable interconnect

 A matrix of logic macro cells that usually consists of

programmable array followed by a flip flop or latch
Programmable Logic Devices
Types of PLDs:
 Read-only Memory(ROM)

 Programmable ROM or PROM

 Electrically Programmable ROM, or EPROM

 An erasable PLD(EPLD)

 electrically erasable PROM, or EEPROM

 UV-erasable PROM , or UVPROM
 mask-programmable ROM

• A mask-programmed PLD usually uses bipolar

Programmable Logic Devices
Logic arrays both have an AND plane and an OR plane

and it may be either be

 A Programmable Array Logic (PAL) – Programmable AND

array and Fixed OR array or

 A programmable logic array (PLA) - Programmable AND array

and Programmable OR array
Programmable ASICs -FPGA
 FPGAs are popular with microsystems designers because they fill a
gap between TTL and PLD design and modern, complex, and often
expensive ASICs.

 FPGAs are ideal for prototyping systems or for low-volume


 FPGA vendors do not need an IC fabrication facility to produce the

chips; instead they contract IC foundries to produce their parts.

 Being fabless relieves the FPGA vendors of the huge burden of

building and running a fabrication plant

 Instead FPGA companies put their effort into the FPGA

architecture and the software, where it is much easier to make a
profit than building chips.
Field-Programmable Gate Arrays
A field-programmable gate array ( FPGA ) or complex PLD
 None of the mask layers are customized
 A method for programming the basic logic cells and the interconnect
 The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops)
 A matrix of programmable interconnect surrounds the basic logic cells
 Programmable I/O cells surround the core
 Design turnaround is a few hours
New Low-Cost Technologies

 FPGA Families  Embedded

 Altera: Cyclone Processors
 Xilinx: Spartan 3  Altera: Nios
 QuickLogic:  Xilinx: MicroBlaze
QuickMIPS, Eclipse II  QuickLogic: MIPS
 Actel: ProASIC Plus  Actel: 8051

 Two dimensional array of customizable logic block
placed in an interconnect array

 Like PLDs programmable at users site

 Implements thousands of gates of logic in a single

 Employs logic and interconnect structure capable of implementing
multi-level logic

 Scalable in proportion with logic removing many of the size limitations

of PLD derived two level architecture
FPGA Architecture
All FPGAs are composed of three fundamental

Logic blocks

I/O blocks

Programmable routing
Programmable Logic Cells

 All FPGAs contain a basic programmable logic cell

replicated in a regular array across the chip
 configurable logic block, logic element, logic module,

logic unit, logic array block, …

 many other names

 There are three different types of basic logic cells:

 multiplexer based

 look-up table based

 programmable array logic (PAL-like)

Logic Cells as Universal Logic
 Logic cells must be flexible, able to implement a
variety of logic functions

 This requirement leads us to consider a variety of

“universal logic components” as basic building blocks

 Multiplexers (MUXs) are one of the most attractive

 not too small a building block

 flexible

 easy to understand
LUT as general logic gate
 LUT is a direct implementation of a Example: 4-lut
function truth-table. INPUTS
A Look up Table is a one bit memory 0000 F(0,0,0,0) store in 1st latch
that produces one output that 0001 F(0,0,0,1) store in 2nd latch
essentially implements a truth table 0010 F(0,0,1,0)
where every input logic produces a 0011 F(0,0,1,1)
logical output. 0011
 Each latch location holds the value of 0110
the function corresponding to one 0111
input combination. 1000
Example: 2-lut 1010
00 0 0 1100
01 0 1 1101
10 0 1 1110
11 1 1 1111
Implements any function of 2 inputs.
Page 31
Structure of LUT
Use Different Input LUTs to Implement A
Boolean Function
A Fictitious FPGA Architecture
(With Multiplexer As Functionally Complete Cell)
 Basic building block
Commercially Available Devices
 Architecture differs from vendor to vendor
 Characterized by
 Structure and content of logic block
 Structure and content of routing resources
 To examine, look at some of available devices
 FPGA: Xilinx (XC4000)
 CPLD: Altera (MAX 5K)
Xilinx FPGAs
 Symmetric Array based; Array
consists of CLBs with LUTs and D-

 N-input LUTs can implement any n-

input boolean function

 Array embedded within the

periphery of IO blocks

 Array elements interleaved with

routing resources (wire segments,
switch matrix and single connection

 Employs SRAM technology

Xilinx XC3000 CLB

Xilinx XC3000 CLB
 A 32-bit look-up table ( LUT )
 CLB propagation delay is fixed (the LUT access time)
and independent of the logic function
 7 inputs to the XC3000 CLB:
 5 CLB inputs (A–E), and
 2 flip-flop outputs (QX and QY)
 2 outputs from the LUT (F and G).
 Since a 32-bit LUT requires only five variables to form
a unique address (32 = 25), there are multiple ways to
use the LUT
 3 LUTs and 2 Flip-flops in a two stage arrangement

 2 Outputs: Can be registered or combinational

 External signals can also be registered

 More of internal signals are available for connections

 Can implement any two independent functions of

four variables or any single function of five variables
XC4000 Logic Block
 Two four-input LUTs that feed a three-input LUT
 Special fast carry logic hard-wired between CLBs
 MUX control logic maps four control inputs C1-C4 into
the four inputs:
 LUT input (H1)
 direct in (DIN)
 enable clock (EC)
 set/reset control for flip-flops (S/R)
 Control inputs C1-C4 can also be used to control the use
of the F’ and G’ LUTs as 32 bits of SRAM
 XC4000 Routing Architecture
XC 4000
 XC4000 Routing Architecture
 Wire segments
 Single length lines
 Spans single CLB
 Connects adjacent CLBs
 Used to connect signals that do not have critical timing requirements
 Double length lines
 Spans two CLBs
 Uses half as much switch as a single length connection
 Long lines
 Low skew; Used for signals such as clock
 Relatively rare resource

 Switch Matrix
 Every line is connected to lines on the other three direction
 Each connection requires six transistors
 Altera generic architecture
 Hierarchical PLD structure
 First level: LABs (Functional
blocks); LAB is similar to SPLDs
 Second Level: Interconnections
among LABs
 LAB consists of
 Product term array
 Product term distribution
 Macro-cells
 Expander product terms
 Interconnection region: PIA
 Example: MAX5K, MAX7K
FLEX 8000 Specifications
• Contains 26-162 Logic Array Block (LAB)

• Each LAB contains 8 Logic Elements (LE) -> 2,500-16,000


• LABs arranged in rows and columns, connected by

FastTrack Interconnect, with I/O Elements (IOE) at the
• 2-level hierarchy (like CPLDs)

• Lowest level consists of LUTs

Altera FLEX 8000 Logic Array Block (LAB)

Each LAB contains:

•8 Logic Elements

•Local Interconnects

•Control signals

•Carry and cascade chains

•Local interconnects have

input from global
FLEX 8000 Logic Element (LE)
LE contains:

• 4-input LUT, can produce any

• function of 4 variables

• Programmable FF, configurable as D,

T, JK, SR, or bypass

• Carry chain
• Cascade chain
Altera MAX Architecture

 Macrocell features:
 Wide, programmable
AND array
 Narrow, fixed OR array
 Logic Expanders
 Programmable inversion

Figure 5.15 The Altera MAX architecture. (a)

Organization of logic and
interconnect. (b) A MAX family
LAB (Logic Array Block). (c) A
MAX family macrocell.
Altera MAX Device Terminology
 Macrocell
 The basic building block of a product term based
 Equivalent to a logic cell (term used to describe the
basic building block of any Altera device)
 Logic Array Block (LAB)
 A group of logic cells
 Each LAB in a MAX device contains 16 macrocells
 Programmable Interconnect Array (PIA)
 Continuous interconnect structure of a MAX 7000
ALTERA MAX Macrocell
MAX 5000 Macrocell

 Three wide AND gate feed an OR gate (Sum of products)

 XOR gate may be used in arithmetic operations or in polarity selection

 One flipflop per macrocell; Outputs may be registered

 Flipflop preset and clear are via product terms; Clock may be either
system clock or internally generated

 Output may be driven out or fedback

 Feedback is both local and global; Local feedback is within macrocell and
is quicker

 Uses antifuse technology

 Based on channeled gate array
 Each logic element (labelled ‘L’)
is a combination of multiplexers
which can be configured as a
multi-input gate
 Fine-grain architecture
ACT 1 Simple Logic Module
 The ACT 1 Logic Module
(LM, the Actel basic logic
 three 2-to-1 MUX
 2-input OR gate
 The ACT 1 family uses just
one type of LM
 ACT 2 and ACT 3 FPGA
families both use two
different types of LM
ACT 1 Simple Logic Module
 An example Actel LM
implementation using
pass transistors (without
any buffering)
ACT 1 Simple Logic Module
 The ACT 1 Logic Module is
two function wheels, an OR
gate, and a 2:1 MUX
 WHEEL(A, B) =MUX(A0, A1,
 MUX(A0, A1, SA)=A0·SA' +
 Each of the inputs (A0, A1, and
SA) may be A, B, '0', or '1'
ACT 1 Simple Logic Module
 Multiplexer-based logic
 Logic functions
implemented by
interconnecting signals
from the routing tracks to
the data inputs and select
lines of the multiplexers.
 Inputs can also be tied to a
logical 1 or 0, since these
signals are always available
in the routing channel.
ACT 1 Simple Logic Module
 8 Input combinational
 702 possible
combinational functions

 2-to-1 Multiplexer A
Y=A•S + B•S B
ACT 1 Simple Logic Module
 Implementation of a
three-input AND gate
ACT 1 Simple Logic Module
 Implementation of S-R

S Q 0

R 1


ACT 2 and ACT 3 Logic Modules
 The C-Module for combinational logic
 Actel introduced S-Modules (sequential) which basically
add a flip-flop to the MUX based C-Module
 ACT 2 S-Module
 ACT 3 S-Module
ACT 2 Logic Module: C-Mod
 8-input combinational
 766 possible
combinational functions
ACT 2 Logic Module: C-Mod
 Example of a Logic
Function Implemented
with the Combinatorial
Logic Module
ACT 3 Logic Module: S-Mod
 Sequential Logic Module
 Up to 7-input function
plus D-type flip-flop with
 The storage element can
be either a register or a
 It can also be bypassed so
the logic module can be
used as a Combinatorial
Logic Module
ACT 2 and ACT 3 Logic Modules
 The equivalent circuit
(without buffering) of
the SE (sequential
ACT 2 and ACT 3 Logic Modules
 The SE configured as a
D flip-flop
FPGA Routing Architecture
Commercial FPGAs can be classified into the four
groups, based on their routing architecture.

 Island – Style FPGA

 Row – Based FPGA
 Sea – Gates FPGA
 Hierarchical FPGA
The Four Classes of FPGA
An Island – Based FPGA
Example channel segmentation distribution
Technology of Programmable Elements
 Vary from vendor to vendor. All share the
common property: Configurable in one of the
two positions – ‘ON’ or ‘OFF’
 Can be classified into three categories:
 SRAM based
 Fuse based
 EPROM/EEPROM/Flash based
 Desired properties:
 Minimum area consumption
 Low on resistance; High off resistance
 Low parasitic capacitance to the attached wire
 Reliability in volume production
SRAM Programming Technology
SRAM Programming Technology
 Employs SRAM (Static RAM) cells
to control pass transistors and/or
transmission gates
 SRAM cells control the
configuration of logic block as well
 Volatile
 Needs an external storage
 Needs a power-on configuration
 In-circuit re-programmable
 Lesser configuration time
 Occupies relatively larger area
Advantages and Disadvantages of
SRAM Programming

 The major advantage of this technology is that FPGA can be

reconfigured (in-circuit) very quickly and can be produced using a
standard CMOS process technology.

 The chip area required by SRAM approach is relatively large.

Anti-fuse Programming Technology
•An anti-fused normally presents a high-impedance state but
can be “fused” into a low-impedance state when
programmed by a high voltage.
•The anti-fuse used in each of FPGAs from different
company differs in construction . But their function is the
Actel anti-fuse – PLICE
Quicklogic anti-fuse - ViaLink
Advantages and Disadvantages
of Anti-fuse Programming
 Anti-fuses chip area are small and Anti-fuses have a
significantly lower on resistance and parasitic
capacitance than transistors, reducing RC delays in the
 The major disadvantages of anti-fuses is that their
manufacture requires modifications to the basic
CMOS process.
EPROM programming Technology
Advantages and Disadvantages of EPROM
and EEPROM Programming
 The major advantage of EPROM is that it requires re-programmable
but do not require external storage. EEPROM can be re-programmed

 A disadvantage of EPROM is that the resistor consumes static power.

And EEPROM requires more chip area and multiple voltage sources.

 An FPGA is similar to several other types of devices which have been around for
quite a while, the difference being that an FPGA is simply much more expandable
and versatile.

 The devices which FPGAs get compared to most often are CPLDs (Complex
Programmable Logic Devices), which are similar in function but typically have way
less logic gates inside them;

 Customizable CPU design is much more feasible with an FPGA. Once upon a
time, CPLDs also had the distinct advantage of retaining their configuration even
when turned off
 When FPGAs first came out, they used simple SRAM to hold their
configuration, which of course would be lost when the device lost power.
 Back then, the FPGA had to be programmed from scratch every time it
was turned on, usually from a separate serial ROM chip.
 But today, FPGAs come in Flash, EPROM, and EEPROM variants, which
will retain configuration, and which can also be re-programmed.
 (Fuse and anti-fuse FPGAs also exist, which act like PROMs in that they
are one-time programmable, and cannot be reprogrammed afterward.

 Despite this, however, most FPGAs still use SRAM for reasons of simplicity (when

you need to reprogram it, it's easier to re-encode a small ROM chip than to
reprogram a large FPGA chip), so count on having to use a separate boot ROM for
the FPGA.

 Use of an FPGA is broadly divided into two main stages: The first is "configuration
mode", the mode in which the FPGA is when you first power it up.

 Once configuration is complete, the FPGA goes into "user mode", its main mode of
operation, where the programmed circuit actually starts functioning.
Interconnection Framework
 Granularity and interconnection structure has
caused a split in the industry

– Fine grained
– Variable length
interconnect segments
– Timing in general is not
predictable; Timing
extracted after placement
and route
Interconnection Framework
– Coarse grained
(SPLD like blocks)
– Programmable crossbar
interconnect structure
– Interconnect structure uses
continuous metal lines
– The switch matrix may or may
not be fully populated
– Timing predictable if fully
– Architecture does not scale well
Field Programmability
 Field programmability is achieved through
switches (Transistors controlled by memory
elements or fuses)
 Switches control the following aspects
 Interconnection among wire segments
 Configuration of logic blocks
 Distributed memory elements controlling the
switches and configuration of logic blocks are
together called “Configuration Memory”
Anti-fuse Programming

 Though implementation differ, all anti-fuse

programming elements share common property
 Uses materials which normally resides in high impedance
 But can be fused irreversibly into low impedance state by
applying high voltage
Anti-fuse Programming Technology
 Very low ON Resistance (Faster implementation of
 Limited size of anti-fuse elements; Interconnects
occupy relatively lesser area
 Offset : Larger transistors needed for programming
 One Time Programmable
 Cannot be re-programmed
 (Design changes are not possible)

 Retain configuration after power off

EPROM, EEPROM or Flash Based
Programming Technology

 EPROM Programming Technology

 Two gates: Floating and Select
 Normal mode:
 No charge on floating gate
 Transistor behaves as normal n-channel transistor
 Floating gate charged by applying high voltage
 Threshold of transistor (as seen by gate) increases
 Transistor turned off permanently
 Re-programmable by exposing to UV radiation
EPROM Programming Technology
 Used as pull-down
 Consumes static
EPROM Programming Technology

 No external storage mechanism

 Re-programmable (Not all!)
 Not in-system re-programmable
 Re-programming is a time consuming task
EEPROM Programming Technology
 Two gates: Floating and Select
 Functionally equivalent to EPROM; Construction
and structure differ
 Electrically Erasable: Re-programmable by
applying high voltage
(No UV radiation expose!)
 When un-programmed, the threshold (as seen by
select gate) is negative!
EEPROM Programming Technology
EEPROM Programming Technology
 Re-programmable; In general, in-system re-
 Re-programming consumes lesser time compared
to EPROM technology
 Multiple voltage sources may be required
 Area occupied is twice that of EPROM!
An Example
 Modulo-4 counter:  Modulo-4 counter: Logic
Specification Implementation
FPGA Implementation of
Modulo-4 Counter
Design Steps Involved in Designing With
 Understand and define design
 Design description
 Behavioural simulation (Source
code interpretation)
 Synthesis
 Functional or Gate level
 Implementation
 Fitting
 Place and Route
 Timing or Post layout simulation
 Programming, Test and Debug