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CMOS VLSI
Design
gclk
3 mm 3.1 mm 0.5 mm
clk1 clk3
clk2
1.3 pF
0.4 pF 0.4 pF
Q1 D2
F1
F2
Combinational Logic
Q1 tpdq tsetup
overhead D2
Q1
F1
CL
D2
sequencing overhead
F2
tcd thold tccq tskew tskew
clk
thold
Q1 tccq
D2 tcd
10
MHz
SpecInt95
100
1
80386 80386
80486
0.1 80486
Pentium
Pentium
Pentium II / III
Pentium II / III
0.01 10
1985 1988 1991 1994 1997 2000 1985 1988 1991 1994 1997 2000
100
Fanout-of-4 (FO4) Inverter Delay (ps)
VDD = 3.3
VDD = 5
500
FO4 inverter delays / cycle
50
VDD = 2.5
200
80386
100 20 80486
Pentium
Pentium II / III
50 10
2.0 1.2 0.8 0.6 0.35 0.25 1985 1988 1991 1994 1997 2000
Process
PLL
– Second-level
clock buffer
– Gater
Route around Typical SLCB
Locations
obstructions
Primary Buffer
2t
D1 Q1 Combinational D2 Q2 Combinational D3 Q3
L1
L2
L3
t pd Tc pdq
Logic 1 Logic 2
sequencing overhead 1
W X
A
B
dynamic static
NAND inverter
clk
clk
t pd Tc 2t pdq
clk clk clk clk clk clk clk clk clk clk
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Static
Static
Static
Static
Static
Static
Latch
Latch
tpdq tpdq
clk
clk
t pd Tc 2tsetup 2tskew
clk clk clk clk clk clk clk clk
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Static
Static
Static
Static
Latch
Latch
tsetup tskew
clk
Dynamic
Dynamic
Dynamic
Static
Static
Static
Static
Latch
Latch
tsetup tskew
Dynamic
Dynamic
a b c d
Static
Static
1 1
2 2
a a
b b
c c
1
2
t pd Tc
1 1 1 1 1 2 2 2
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Static
Static
Static
Static
Static
Static
Static
Static
Phase 1 Phase 2
1
2
3
4
1 1 2 2 3 3 4 4
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Static
Static
Static
Static
Static
Static
Static
Static
Phase 1 Phase 2 Phase 3 Phase 4
en clk
1
2
3
4