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Ultralow-Voltage High-Speed

ANALOG TO DIGITAL
converter(Flash ADC)
UJJAYINI DEBNATH
03102072017
M.tech, VLSI design
Introduction
• analog-to-digital converters (ADCs) are required for
many applications, such as disk drive front-ends,
high-speed backplanes, ultra wideband receivers,
and millimeter-wave receivers
• Conventionally, the highly digital flash architecture
is the most suitable candidate for high-speed
applications “because of its low latency”
FLASH ADC

A flash ADC (also known as a direct-


conversion ADC) is a type of an alog-to-digital
converter that uses a linear voltage ladder
with a comparator at each "rung" of the
ladder to compare the input voltage to
successive reference voltages.
Why FLASH ADCs are fast?
• Flash analog-to-digital converters, also known as
parallel ADCs, are the fastest way to convert an
analog signal to a digital signal.
• Flash ADCs are ideal for applications requiring very
large bandwidth, but they consume more power
than other ADC architectures and are generally
limited to 8-bit resolution.
Implementation

A 2-bit flash ADC example implementation with bubble error


correction and digital encoding
Implementation

• Flash ADCs have been implemented in many


technologies, such as BJT, complementary
metaloxide FET (CMOS)
• Implementations consisted of a reference ladder of well
matched resistors connected to a reference voltage.
• Each tap at the resistor ladder is used for one comparator
• thus generates a logical 0 or 1 depending on whether the
measured voltage is above or below the reference
voltage of the resistor tap.
• Offset calibration-A test signal is applied, and the offset
of each comparator is calibrated to below the LSB value
of the ADC.
What is RESOLUTION in ADCs?
• (ADC) resolution can be used to describe the general
performance of an ADC.
• Resolution and accuracy are terms that are often
interchanged.
• The resolution of an A/D converter (ADC) is specified
in bits and determines how many distinct output
codes (2n) the converter is capable of producing.
Energy and resolution graph

Due to its similarities to digital circuits, supply voltage lowering is


an effective method in reducing its power consumption
ULTRALOW-VOLTAGE STRATEGY
• A sampling circuit is an essential part of an ADC.
Moreover, it also determines the fundamental
energy consumption for a given resolution as
expressed below –
Es = 24kT 22N

• where Es is the sampling energy limited by the


thermal noise, k is the Boltzmann
constant(1.3806*10^-3 m^2 kg s^-2 k^-1), T is the
ambient temperature, and N is the resolution.
Application

• like radar detection, wideband


radio receivers, electronic test equipment,
and optical communication links,
• Also a small flash ADC circuit may be present
inside a delta-sigma modulation loop.
• Flash ADCs are also used in NAND
flash memory, where up to 3 bits are stored
per cell as 8 voltages level on floating gates.
Benefits and drawbacks

• Flash converters are extremely fast compared


to many other types of ADCs
• a flash converter is also quite simple
REFERENCE
1. Samaneh Babayan-Mashhadi, Reza Lotfi “Analysis and Design of a Low-Voltage Low-Power Double-Tail
Comparator”, IEEE Trans. On Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 2, February 2014.
2. Harjjot Singh Bindra, Christiaan E. Lokin, Daniel Schinkel, Anne-Johan Annema, Bram Nauta, “A 1.2-V
Dynamic Bias Latch-type Comparator in 65-nm CMOS With 0.4-mV Input Noise”, IEEE Journal Of Solid
State Circuits, Vol. 53, No. 7, July 2018.
3. Behzad Razavi and Bruce A. Wooley, “Design Techniques For High-Speed, High-Resolution Comparators”,
IEEE Journal Of Solid-State Circuits, Vol. 27, No. 12, December 1992.
4. L. Ravezzi and D. Stoppa and G.-F Dalla Betta, “Simple High-speed CMOS Current Comparator”, IEEE 1997
Electronics Letters Online No: 19971250, 19 August 1997.
5. B.B.A. Fouzy, MBI Reaz, MAS Bhuiya, M.T.J. Badal, F.H. Hashim,“Design of a Low Power High Speed
Comparator In 0.13 μm CMOS”, International conference on advances in Electrical, Electronic & System
Engineering, 14-16 Nov, 2016.
6. Mohamed Abbas,Yasuo Furukawa, Satoshi Komatsu, Takahiro. J. Yamaguchi. Kunihiro Ajada; “Clocked
Comparator for High Speed Application in 65nm Technology”, IEEE Asian Solid-State Circuits Conference
8-10 November, 2010.
7. A. Manikandan, J.Ajayan,C.Kavin Avasan, S. Karthik, K.Vivek; “ High Speed low power 64 bit coparison
Based domino Logic.” IEEE sponsored 2nd International Conference on Electronics & Communication
Systems (ICECS), 2015.
8. Rahul jain, Animesh K. Dubey, Vikrant Varshing Rajendra Kumar Nagaria, “Design of low power high
speed Double fast Dynamic CMOS Comparator using Novel Latch Structure” IEEE Uttar Pradesh Section
International Conference, 26-28 October, 2017.
9. Had Aghabeigi, Mehdi Tafaripanah, “High Speed low power Voltage Comparator .18um CMOS process
for Flash ADCs” International Conference on knowledge based Engineering & Innovation (KBFJ), Dec 22nd,
2017.
REFERENCE

10. Satyabrata Nanda, Avipsa S. Panda. “Design of Conventional Three-stage CMOS comparator in 90nm CMOS
Technology and comparative analysis with its counterparts”, International Conference on Smart Sensor and
Systems (IC-SSS), 2015.
11. Iffa Sharauddin and L.Lee, “Modified SR Latch in Dynamic comparator for Ultra-low Power SAR ADC”, IEEE
International Circuits and Systems Symposium (ICSYS), 2015.
12. Sudakar S. Chauhan, S. Manabala, S.C. Bose and R. Chandel, “A New Approach to Design Low- Power
CMOS Flash A/D Converter”, International Journal of VLSI Design &Communication Systems (VLSICS) Vol. 2,
No. 2, June 2011.
13. Hadi Aghabeigi, Mchdi Jafaripanah, “High Speed Low-power Voltage Comparator in 0.18 um CMOS Process
for Flash ADCs”, 4th International Conference of Knowledge-Based Engineering and Innovation (KBEI-2017).
14. Felix Lang, Thomas Alpert , Damir Ferenci, Markus Grozing, Menfred Berroth, “A 6 Bit 25 GS/s Flash
Intepolating ADC in 90 nm CMOS Technology”, Institute of Electrical and Optical Communication Engineering
15. "Integrated Analog-to-Digital and Digital-to-Analog Converters", R. van de Plassche, ADCs, Kluwer Academic
Publishers, 1994.
16. "A Precise Four-Quadrant Multiplier with Subnanosecond Response", Barrie Gilbert, IEEE Journal of Solid-
State Circuits, Vol. 3, No. 4 (1968), pp. 365–373

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