CONTENTS

 Introduction
 Literature Survey
 Scope of the project
 Block Diagram
 Description
 Advantages
 Tools Used
 References
INTRODUCTION
 In the majority of digital signal processing (DSP)
applications the critical operations are the
multiplication and accumulation. Real-time signal
processing requires high speed and high throughput
Multiplier-Accumulator (MAC) unit that consumes
low power, which is always a key to achieve a high
performance digital signal processing system.
LITERATURE SURVEY
 In general, a multiplier uses Booth’s algorithm and
array of full adders (FAs), or Wallace tree instead of
the array of FA’s., i.e., this multiplier mainly consists of
the three parts: Booth encoder, a tree to compress the
partial prod
 A new architecture for a high-speed MAC is proposed.
In this MAC, the computations of multiplication and
accumulation are combined and a hybrid-type CSA
structure is proposed to reduce the critical path and
improve the output rateucts such as Wallace tree, and
final adder
Overview
 A multiplier can be divided into three operational
steps. The first is radix-2 Booth encoding in which a
partial product is generated from the multiplicand X
and the multiplier Y.
 The second is adder array or partial product
compression to add all partial products.
 The last is the final addition in which the process to
accumulate the multiplied results is included.
Basic Arithmetic steps for MAC
Simple MAC
Proposed MAC Algorithm
BLOCK DIAGRAM
Example:
 Find 3 × (−4), with m = 3 and r = −4, and x = 4 and y = 4:
 A = 0011 0000 0
 S = 1101 0000 0
 P = 0000 1100 0
 Perform the loop four times :
 P = 0000 1100 0. The last two bits are 00.
 P = 0000 0110 0. Arithmetic right shift.
 P = 0000 0110 0. The last two bits are 00.
 P = 0000 0011 0. Arithmetic right shift.
 P = 0000 0011 0. The last two bits are 10.
 P = 1101 0011 0. P = P + S.
 P = 1110 1001 1. Arithmetic right shift.
 P = 1110 1001 1. The last two bits are 11.
 P = 1111 0100 1. Arithmetic right shift.
 The product is 1111 0100, which is −12.
DESCRIPTION
 Booth Encoder
 CSA & accumulator
 Final Adder
Booth Encoder
 Booth multiplication is a technique that allows for smaller, faster
Multiplication circuits, by recoding the numbers that are multiplied. It is the
standard technique used in chip design, and provides significant
improvements over the "long multiplication" technique.
Reducing the Number of Partial Products
It is possible to reduce the number of partial products by half, by using the
technique of radix 4 Booth encoding. The basic idea is that, instead of shifting
and adding for every column of the multiplier term and multiplying by 1 or 0,
we only take every second column, and multiply by ±1, ±2, or 0, to obtain the
same results
Partial Product 0 = Multiplicand * -1, shifted left 0 bits (x -1)
Partial Product 1 = Multiplicand * 2, shifted left 2 bits (x 8)

The advantage of this method is the halving of the number of partial products.
This is important in circuit design as it relates to the propagation delay in the
running of the circuit, and the complexity and power consumption of its
implementation.
Signed Multiplication Algorithm
Multiplication calculations by hand
Multiplication Operation in
hardware
Booth partial products Generation
Booth partial product selector logic
CSA
 A carry-save adder is a type of Digital adder, used in computer
micro architecture to compute the sum of three or more n-bit
numbers in binary. It differs from other digital adders in that it
outputs two numbers of the same dimensions as the inputs, one
which is a sequence of partial sum bits and another which is a
sequence of carry bits.
 The carry-save unit consists of n Full Adders, each of which
computes a single sum and carry bit based solely on the
corresponding bits of the three input numbers.

 Psi = ai xor bi xor ci;

Basic CSA
Proposed CSA
Final Adder
 The Final Adder is Also Carry Lockheed Adder.
 A carry-lookahead adder (CLA) is a type of adder used
in digital Logic . A carry-lookahead adder improves speed
by reducing the amount of time required to determine
carry bits. It can be contrasted with the simpler, but usually
slower,ripple carry adder for which the carry bit is
calculated alongside the sum bit, and each bit must wait
until the previous carry has been calculated to begin
calculating its own result and carry bits (see adder for
detail on ripple carry adders). The carry-lookahead adder
calculates one or more carry bits before the sum, which
reduces the wait time to calculate the result of the larger
value bits.
Carry Look Ahead Adder
 Thus, one can write,
COUT = Ci+1 = Ai.Bi + (Ai Å Bi).Ci. (1)
 The "Å" stands for exclusive OR or XOR. One can write
this expression also, as
Ci+1 = Gi + Pi.Ci (2)
in which
Gi = Ai.Bi (3)
Pi = (Ai Å Bi) (4)
are called the Generate and Propagate term, respectively.
 C1 = G0 +P0.C0

 C2 =G1 +P1.C1 =G1 +P1.G0 +P1.P0.C0

 C3 = G2 +P2.G1 +P2.P1.G0 +P2.P1.P0.C0

 C4 = G3 +P3.G2 +P3.P2.G1 +
P3P2.P1.G0 +P3P2.P1.P0.C0
CLA Architecture
Design Flow
Applications
 DSP
 DIP
 Computer
 Medical Appilications
Simulation Results
Synthesis Results
Design Summary
 =========================================================================
 * Final Report *
 =========================================================================
 Final Results
 RTL Top Level Output File Name : mac_top.ngr
 Top Level Output File Name : mac_top
 Output Format : NGC
 Optimization Goal : Speed
 Keep Hierarchy : NO

 Design Statistics
 # IOs : 32

 Cell Usage :
 # BELS : 185
 # LUT2 :6
 # LUT3 : 67
 # LUT4 : 90
 # MUXF5 : 22
 # IO Buffers : 32
 # IBUF : 16
 # OBUF : 16
 =========================================================================

 Device utilization summary:

 ---------------------------
 =========================================================================

 Device utilization summary:

 ---------------------------

 Selected Device : 3s50atq144-4

 Number of Slices: 90 out of 704 12%

 Number of 4 input LUTs: 163 out of 1408 11%
 Number of IOs: 32
 Number of bonded IOBs: 32 out of 108 29%

 ---------------------------
 Partition Resource Summary:
 ---------------------------

 No Partitions were found in this design.

 ---------------------------

 =========================================================================
 TIMING REPORT
Conclusion
A 8x8 multiplier-accumulator (MAC) is presented in
this work. A Radix 4 Modified Booth multiplier circuit is
used for MAC architecture. Compared to other circuits, the
Booth multiplier has the highest operational speed and less
hardware count. The basic building blocks for the MAC
unit are identified and each of the blocks is analyzed for its
performance.
Power and delay is calculated for the blocks. 1-bit MAC
unit is designed with enable to reduce the total power
consumption based on block enable technique.
The MAC unit designed in this work can be used in
filter realizations for High speed DSP applications.
TOOLS USED
 Modelsim 6.5 for Simulation
 Xilinx ISE 10.1 for Synthsis

 For Design VERILOG 2005

References
 J. J. F. Cavanagh, Digital Computer Arithmetic. New York: McGraw-
 Hill, 1984.
 Information Technology-Coding of Moving Picture and Associated
Autio, MPEG-2 Draft International Standard, ISO/IEC 13818-1, 2, 3, 1994.
 JPEG 2000 Part I Fina1119l Draft, ISO/IEC JTC1/SC29 WG1.
 O. L. MacSorley, “High speed arithmetic in binary computers,” Proc.
IRE, vol. 49, pp. 67–91, Jan. 1961.
 S. Waser and M. J. Flynn, Introduction to Arithmetic for Digital Systems
Designers. New York: Holt, Rinehart and Winston, 1982.
 A. R. Omondi, Computer Arithmetic Systems. Englewood Cliffs, NJ:
Prentice-Hall, 1994.
 A. D. Booth, “A signed binary multiplication technique,” Quart. J.
Math., vol. IV, pp. 236–240, 1952.