Ntroarchitecture Pin Diagram Modes Addressing Mode

CSE-221 Microprocessor and Interfacing
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Origin of Microprocessors

• Microprocessor is the greatest invention of the 20th Century
• Evolution started from the earlier mechanical calculating devices-
In 1930
• In 1950-Replaced by Vacuum tubes-Replaced by transistors
• Transistor Technology led to the introduction of minicomputer in
the 1960s and the PC revolution in the 1970s
• TT led to the development of complex devices called ICs

History-Events leading to development of
the microprocessor
• December 23, 1947, John Bardeen, William

Shockley, and Walter Brattain develop the
transistor at Bell Labs.
• Followed by 1958 invention of the integrated
circuit (IC) by Jack Kilby of Texas Instruments.
• IC led to development of digital integrated
circuits in the 1960s.
• First microprocessor developed at Intel
Corporation in 1971.
– MPU later evolved as an IC and was designed to fetch
instructions and execute the predefined arithmetic
and logic functions.
– Intel was the 1st MPU producer and has been holding
a large share of the world market for this product.
– Evolution of the microprocessor is categorized into
five generations.
– First generation (1971-1973)
• Referred to as the first generation systems.
• Processed Instruction serially

Origin of Microprocessors-First
generation(1971-1973)
– 1st microprocessor-4004-introduced in 1971
– 4-bit 4004 microprocessors ran at 108kHz and
contained 2300 transistors
– Fabrication using p-channel MOS tech.
– low cost, slow speed and not compatible with TTL
– In 1972, Intel made 8-bit 8008 and 8080 µP.

Origin of Microprocessors-Second
– It marked the beginning of very efficient 8-bit µP.
– Some of the popular processors were Motorola’s 6800
and 6809, Intel’s 8085, Zilog’s Z80.
– 2nd generation devices- use of newer semiconductor
tech to fabricate chips.
– By using n-channel (NMOS) tech.
– Advantages: Five-fold increase in instruction
execution speed and higher chip densities.

Origin of Microprocessors-Third
• 3rd generation as dominated by Intel’s 8086 and Zilog’s Z8000.
• 16-bit processors with minicomputer-like performance
• Tech of 16-bit arithmetic and pipelined instruction
• IC transistor counts- 250,000
• Example:Motorola’s MC68020-On chip cache was incorporated for
the first time and pipeline was increased to five or more stages.
• Design techniques-HMOS tech.
• Advantages:
– Speed-power product is four times better than that of the NMOS.
– Can accommodate twice the circuit density of NMOS.

Origin of Microprocessors-Fourth
• 4th generation designs contains more than a
million transistor in a single package.
• Beginning of 32-bit µP’s.
• Intel 80386 and Motorola 68020/68030 were
introduced
• Fabrication-High density/High speed
CMOS(HCMOS)

Origin of Microprocessors-Fifth
generation(1995-till date)
– It employs decoupled super scalar processing.
– Design contains more than 10 million transistors
– Introduction of an on-chip functionalities
– High speed memory I/O devices, intro of 64-bit µP’s
– Intel lead the show here with Pentium, Celeron, Dual-
and quad-core and very recently i3,i5,i7 working with
up with up to 3.33 GHz Turbo Boost speed.

Timeline of µP evolution
General Purpose
processors Year Clock speed Transistors
Intel 4004 1969 108 KH z 2300
Intel 8008 1972 800 KH z 3500
Intel 8080 1974 2 MH z 4500
Intel 8085 1976 3-5MHz 6500
Intel 8086 1978 4.47 MH z 29000
Intel 8088 1981 4.47 MH z 29000
Intel 286 1982 12 MH z 134000

General Purpose
Intel 386 1985 16 MH z 275000
Intel 486 1989 25 MH z 1,200,000
Intel Pentium 1993 66 MH z :3,300,000
Intel Pentium pro 1995 200 MH z 5,500,000
Intel Pentium || 1997 300 MH z 7,500,000
Intel Pentium ||| 1999 500 MH z 9,500,000
Intel Pentium 4 2000 1 GH z 15,500,000

General Purpose
Intel Pentium D 2005 3.6 GH z 47,500,000
Intel Core 2 / Quad 2006 3.6 GH z 214,500,000

Variants530 – 2.93 GHz
Hyper-Threading - 540 –
3.06 GHz L1 cache 512 Kb
L2 cache 4 MB L3 cache
Core i3 2007
Variants650/655K –
3.2 GHz Hyper-Threading
Turbo Boost - 660/661 –
Core i5 2008 3.33 GHz
Variants940XM Extreme
Edition -
2.13 GHz/3.33 GHz Turbo
Core i7 2010 Boost

Applications
• The microprocessor has made possible the
– inexpensive hand-held electronic calculator, the digital
wristwatch, and the electronic game.
• Microprocessors are used to control consumer electronic
devices, such as the
– programmable microwave oven and videocassette recorder;
– to regulate gasoline consumption and antilock brakes in
automobiles;
– to monitor alarm systems; and to operate automatic tracking and
– targeting systems in aircraft, tanks, and missiles and to control
radar arrays that track and identify aircraft, among other defense
applications.
Programming Advancements
• Once programmable machines developed, programs and
programming languages began to appear.
• Stored in the computer memory system as groups of instructions
called a program
• Mathematician John von Neumann first modern person to develop
a system to accept instructions and store them in memory
• UNIVAC -early 1950s, assembly language was used to simplify
entering binary code.
• Assembler allows programmer to use mnemonic codes…
– such as ADD for addition
• In place of a binary number.
– such as 0100 0111
• Assembly language an aid to programming
Highlights
• The worlds first PC ran on an Intel 8088

microprocessor.
• Various other companies such as
Motorola,NEC,Mitsubishi,Siemens,AMD,Toshiba
and Texas Instruments also manufacture
processor chips.
• These companies have their own chips and
architectures in addition to the regular Intel
based architectures.
8086-Microprocessor Architecture
• In 1978, Intel released its first 16-bit microprocessor-
8086.
• It executes the instructions at 2.5MIPS
• Execution time for one instruction is 400ns(1/MIPS).
• 8086 can address 1MB(1MB=220 bytes) of memory-20 bit
address bus
• Width of the data bus is 16bits
• Feature- Small six-byte instruction queue
– Instruction fetched from the memory are placed before they
are executed.

• Functional block diagram of 8086, subdivided into the following
two units:
1. Execution unit (EU)
2. Bus interface unit (BIU)
Execution unit: It includes the ALU, eight 16-bit general purpose
registers, a 16-bit flag register, and a control unit
Bus Interface unit: It includes an adder for address calculations,
four-16 bit segment registers(CS,DS,SS,ES), a 16-bit instruction
pointer(IP), a six-byte instruction queue, and bus control logic

• Components in BIU:
– Segment Register
– The Instruction pointer
– Address generation Register
– Bus control logic
– Instruction Queue
• Components in EU:
– Arithmetic logic Unit: ALU
– Status and control logic
– General purpose registers
– Temporary operand registers

• Address bus (20 bits)
AH AL General purpose
BH BL register 
CH CL
Execution Unit
DH DL
(EU) Data bus
SP CS (16 bits)
Segment
BP register DS
SI SS
DI ALU Data bus ES
(16 bits) IP
Bus
control
ALU Instruction Queue External bus
EU
control
Flag register
Bus Interface Unit (BIU)

General Purpose Registers
15 8 7 0
AX AH AL Accumulator
BX BH BL Base
Data Group
CX CH CL Counter
DX DH DL Data
SP Stack Pointer
BP Base Pointer
Pointer and
Index Group
SI Source Index
DI Destination Index

– General Purpose registers can be used to store 8-bit

or 16-bit data during program execution. In addition
each register has the following function:
• AX/AL:
– It is used as a accumulator.
– It is used in the multiply,divide, and input/output operations, and in
some decimal and ASCII adjustment instructions.
• BX:
– It holds the offset address of a location in the memory. It is also
used to refer to the data in the memory using the look-up table
technique, with the help of the XLAT instruction.

– CX/CL:
• CX is used to hold the count value while executing the repeated string
instruction and the LOOP instruction. (REP/REPE/REPNE).
• CL- Used to hold the count value while executing the shift/rotate
instructions.
– DX:
• Used to hold a part of the result during a multiplication operation and a
part of the dividend before a division operation.
• Used to hold the I/O device address while executing the IN and OUT
instructions.
– Offset: This is a 16-bit number that is added to the base address
of a segment, to select a byte of instruction or data from the
memory

SP:
– Stack Pointer is used to hold the offset address of the data stored at the top
of the stack segment.
– SP is used along with the SS register to decide the address at which the data
is to be pushed or popped, during the execution of the PUSH or POP
instruction, respectively.
BP:
– BP register is called base pointer
– Used to hold the offset address of the data to be read from or written into
the stack segment.
SI:
– Source index register
– Used to hold the offset address of the source data in the data segment,
while executing string instructions.
DI: destination data

Segment registers
– Segment refers to a portion of the memory
– Function of these registers is to indicate the starting or base
address of the code segment, data seg, stack seg, extra seg
respectively in the memory.
– CS contains Instruction of a program, DS-Data of a program,
SS holds the stack of the program, w hich is needed while
executing the CALL and RET instructions and also to handle
interrupts, ES is an additional data segment
– Data, code or stack for a program is stored
– In 8086, the max size of a segment can be 64KB and the min
size can be even 1 byte
– A segment always begins at a memory address divisible by 16.
Eg: CS(64K(MAX) (20000H-2FFFFH), Total(1MB)(00000H-FFFFFH)

Segment registers and default offset
registers in the 8086
Segment registers Default offset registers
CS IP
DS BX,SI,DI, 8-or 16-bit

displacement
SS SP and BP
ES DI for string instruction

Segmented Memory

Segmented Memory

Address Calculation

Address Calculation

Address Calculation

Address Calculation

Flag Register
– A flag is a flip-flop which indicates some condition produced by
the execution of an instruction, or controls certain opertions of
the EU.

A trap is an
Flag Register exception in a user
process. It's caused
by division by zero
or invalid memory
access.
It's also the usual
way to invoke a
kernel routine (a
system call)
because those run
with a higher
priority than user
code.
Handling is
synchronous (so
the user code is
suspended and
Interrupt(Time delay) continues
TF= 1; 8086 gets interrupt TF=0; No interrupt afterwards).

Flag Register

Flag Register
• Examples
Sign Flag:
+13=00001101
+9 =00001001
+22=00010110 (Sign bit is 0; so result is positive)
+13=00001101
-9 =11110111 (2’s complement for -9 with sign bit
+4=100000100(Ignore Carry; Sign bit is 0 so result is positive)
+9 =00001001
-13=11110011 (2’s complement for -13 with sign bit
-4 = 11111100 sign bit is 1; negative)
00000011 Invert each bit
1( add 1)
00000100( -4; magnitude)
Flag Register
Note: Range of Signed Numbers that can be represented with 8 binary
bits; In normal codes, the range is 0 to +127 and from -1 to -128
Note: 01111111 +127
.
.
00000001 +1
00000000 Zero
11111111 -1
.
.
10000001 -127
10000000 -128

Flag Register
• If register AL=7FH and the instruction ADD
AL,1
• Result:
– AL = 80H ; 7FH+1=80H
– CF = 0 ; No carry out of bit 7
– PF = 0 ; 80H has an odd no of logic 1’s
– AF = 1 ; Carry out of bit 3 into bit 4
– ZF = 0 ; Result is not 0
– SF = 1 ; Bit 7 is set
– OF = 1 ; Result(+128) exceeds the capacity of register AL
Internal Arch of 8086
• 8086 has two blocks BIU and EU. The BIU performs all bus operations such as
instruction fetching, reading and writing operands for memory and calculating
the addresses of the memory operands. The instruction bytes are transferred to
the instruction queue.
• EU executes instructions from the instruction system byte queue.
• Both units operate asynchronously to give the 8086 an overlapping instruction
fetch and execution mechanism which is called as Pipelining. This results in
efficient use of the system bus and system performance.
• BIU contains Instruction queue, Segment registers, Instruction pointer, Address
adder.
• EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index
register, Flag register.

BUS INTERFACE UNIT:
• It provides a full 16 bit bidirectional data bus and 20 bit address bus.
• The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and
Bus control.
– The BIU uses a mechanism known as an instruction stream queue to implement a
pipeline architecture. This queue permits prefetch of up to six bytes of instruction
code. When ever the queue of the BIU is not full, it has room for at least two more
bytes and at the same time the EU is not requesting it to read or write operands from
memory, the BIU is free to look ahead in the program by prefetching the next
sequential instruction.
– These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle.
– After a byte is loaded at the input end of the queue, it automatically shifts up through
the FIFO to the empty location nearest the output

• The EU accesses the queue from the output end. It reads one instruction byte
after the other from the output of the queue. If the queue is full and the EU is
not requesting access to operand in memory.
• These intervals of no bus activity, which may occur between bus cycles are
known as Idle state.
• If the BIU is already in the process of fetching an instruction when the EU
request it to read or write operands from memory or I/O, the BIU first completes
the instruction fetch bus cycle before initiating the operand read / write cycle.
• The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus. This address is formed by
adding an appended 16 bit segment address and a 16 bit offset address.
• For example: The physical address of the next instruction to be fetched is
formed by combining the current contents of the code segment CS register and
the current contents of the instruction pointer IP register.
• The BIU is also responsible for generating bus control signals such as those for
memory read or write and I/O read or write.

EXECUTION UNIT :
• The Execution unit is responsible for decoding and executing all instructions. The EU
extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary,passes them to the BIU and requests it to perform the read or write
bus cycles to memory or I/O and perform the operation specified by the instruction on
the operands.
• During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.
• If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.
• When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
• Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

Pin diagram

Pin diagram-Minimum and Maximum Modes:
• The minimum mode is selected by applying logic 1 to

the MN / MX# input pin. This is a single microprocessor
configuration.
• The maximum mode is selected by applying logic 0 to
the MN / MX# input pin. This is a multi micro processors
configuration.

Pin diagram
• It is a 16 bit μp.
• 8086 has a 20 bit address bus can access upto 2^20 memory locations ( 1 MB) .
• It can support upto 64K I/O ports.
• It provides 14, 16-bit registers.
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
• It requires single phase clock with 33% duty cycle to provide internal timing.
• 8086 is designed to operate in two modes, Minimum and Maximum.
• It can prefetches upto 6 instruction bytes from memory and queues them in
order to speed up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package.

Pin diagram-Explaination

Pin diagram-Explaination

Pin diagram-Explanation

Min and Max
• Minimum mode operation is similar to that of the Intel 8085A
microprocessor, while maximum mode operation is new &
specially designed for the operation of the 8087 arithmetic
coprocessor

Minimum Mode Interface
• When the Minimum mode operation is selected, the 8086 provides all control
signals needed to implement the memory and I/O interface.
• The minimum mode signal can be divided into the following basic groups :
address/data bus, status, control, interrupt and DMA.
• Address/Data Bus : These lines serve two functions. As an address bus is 20 bits long
and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A
20bit address gives the 8086 a 1Mbyte memory address space. More over it has an
independent I/O address space which is 64K bytes in length.
• The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0
through A15 respectively. By multiplexed we mean that the bus work as an address
bus during first machine cycle and as a data bus during next machine cycles. D15 is
the MSB and D0 LSB.
• When acting as a data bus, they carry read/write data for memory, input/output
data for I/O devices, and interrupt type codes from an interrupt controller.


• Status signal : The four most significant address lines A19
through A16 are also multiplexed but in this case with status
signals S6 through S3. These status bits are output on the bus at
the same time that data are transferred over the other bus lines.
• Bit S4 and S3 together from a 2 bit binary code that identifies
which of the 8086 internal segment registers are used to generate
the physical address that was output on the address bus during
the current bus cycle.
• Code S4S3 = 00 identifies a register known as extra segment
register as the source of the segment address.

• Status line S5 reflects the status of another internal characteristic of the 8086. It
is the logic level of the internal enable flag. The last status bit S6 is always at the
logic 0 level.
• Control Signals : The control signals are provided to support the 8086 memory
I/O interfaces. They control functions such as when the bus is to carry a valid
address in which direction data are to be transferred over the bus, when valid
write data are on the bus and when to put read data on the system bus.
• ALE is a pulse to logic 1 that signals external circuitry when a valid address word
is on the bus. This address must be latched in external circuitry on the 1-to-0
edge of the pulse at ALE.
• Another control signal that is produced during the bus cycle is BHE bank high
enable. Logic 0 on this used as a memory enable signal for the most significant
byte half of the data bus D15 through D8 during read/write operation.These
lines also serves a second function, which is as the S7 status line(always 1)
• Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in
progress and in which direction data are to be transferred over the bus.
• The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking
place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O
operation.
• The direction of data transfer over the bus is signaled by the logic level output at DT/R.
When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the
transmit mode. Therefore, data are either written into memory or output to an I/O
device.
• On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This
corresponds to reading data from memory or input of data from an input port.
• The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in
progress. The 8086 switches WR to logic 0 to signal external device that valid write or
output data are on the bus.
• On the other hand, RD indicates that the 8086 is performing a read of data of the bus.
During read operations, one other control signal is also supplied. This is DEN ( data
enable) and it signals external devices when they should put data on the bus.(data Is
transferred through databus of 8086-{signal-logic 0}; No data flows in data bus{Logic 1}
• There is one other control signal that is involved with the memory and I/O interface.
This is the READY signal.
• READY signal is used to insert wait states into the bus cycle such that it is extended by a
number of clock periods. This signal is provided by an external clock generator device
and can be supplied by the memory or I/O subsystem to signal the 8086 when they are
ready to permit the data transfer to be completed.
• Interrupt signals : The key interrupt interface signals are interrupt request (INTR) and
interrupt acknowledge ( INTA).
• INTR is an input to the 8086 that can be used by an external device to signal that it need
to be serviced.
• Logic 1 at INTR represents an active interrupt request. When an interrupt request has
been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0
at the INTA output.
• The TEST input is also related to the external interrupt interface. Execution of a WAIT
instruction causes the 8086 to check the logic level at the TEST input.
• If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086
no longer executes instructions, instead it repeatedly checks the logic level ofthe TEST
input waiting for its transition back to logic 0.

• As TEST switches to 0, execution resume with the next instruction in the program. This
feature can be used to synchronize the operation of the 8086 to an event in external
hardware.
• There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI
and the reset interrupt RESET.
• On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service
routine. The RESET input is used to provide a hardware reset for the 8086. Switching
RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service
routine
• DMA Interface signals :The direct memory access DMA interface of the 8086 minimum
mode consist of the HOLD and HLDA signals.
• When an external device wants to take control of the system bus, it signals to the 8086
by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the
8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3
through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state. The
8086 signals external device that it is in this state by switching its HLDA output to logic 1
level.

Maximum Mode Operation
– it is selected by grounding MN/MX
– differs from minimum in that some of the control signals must
be externally generated, so that it is need an external bus
controller, 8288 bus controller
– the maximum mode is used only when the system contains
external coprocessors such as the 8087 arithmetic coprocessor

Maximum Mode Interface
• When the 8086 is set for the maximum-mode configuration, it provides signals for
implementing a multiprocessor / coprocessor system environment.
• By multiprocessor environment we mean that one microprocessor exists in the system
and that each processor is executing its own program.
• Usually in this type of system environment, there are some system resources that are
common to all processors.
• They are called as global resources. There are also other resources that are assigned to
specific processors. These are known as local or private resources.
• Coprocessor also means that there is a second processor in the system. In this two
processor does not access the bus at the same time.
• One passes the control of the system bus to the other and then may suspend its
operation.
• In the maximum-mode 8086 system, facilities are provided for implementing allocation
of global resources and passing bus control to other microprocessor or coprocessor.


• The 8288 Bus Controller

– it must be used in the maximum mode to provide
the control bus signals to the memory and I/O
– this is because the maximum mode operation of
the 8086/8088 removes some of the systems
control signal lines in favor of control signals for
the coprocessors
– the 8288 reconstructs these removed control
signals

• 8288 Bus Controller – Bus Command and Control Signals: 8086 does not directly provide all the
signals that are required to control the memory, I/O and interrupt interfaces.
• Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086.
Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit
bus status code identifies which type of bus cycle is to follow.
• S2S1S0 are input to the external bus controller device, the bus controller generates the
appropriately timed command and control signals.
• The 8288 produces one or two of these eight command signals for each bus cycles. For
instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read
cycle is to be performed.
• In the code 111 is output by the 8086, it is signaling that no bus activity is to take place.
• The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide
the same functions as those described for the minimum system mode. This set of bus
commands and control signals is compatible with the Multibus and industry standard for
interfacing microprocessor systems.


• The output of 8289 are bus arbitration signals: bus busy (BUSY), common bus request
(CBRQ), bus priority out (BPRO), bus priority in (BPRN), bus request (BREQ) and bus clock
(BCLK).
• They correspond to the bus exchange signals of the Multibus and are used to lock other
processor off the system bus during the execution of an instruction by the 8086.
• In this way the processor can be assured of uninterrupted access to common system
resources such as global memory.
• Queue Status Signals : Two new signals that are produced by the 8086 in the maximum-
mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue
status code, QS1QS0.
• Following table shows the four different queue status.

Maximum Mode Interface-Queue
status code

• Local Bus Control Signal – Request / Grant Signals: In a

maximum mode configuration, the minimum mode HOLD,
HLDA interface is also changed. These two are replaced by
request/grant lines RQ/ GT0 and RQ/ GT1, respectively.
They provide a prioritized bus.

Addressing Modes of 8086
• Every instruction of a program has to operate on a data. The

method of specifying the data to be operated by the instruction is
called addressing.
• The 8086 has 12 addressing modes and they can be classified into
following five groups.
• Group 1: Addressing modes for register and immediate data
• Group 2:Addressing modes for memory data
• Group3: Addressing modes for I/O ports
• Group4: Relative addressing mode
• Group5:Implied addressing mode

• Group1:
– Register addressing, Immediate addressing
• Group2:
– Direct addressing, register indirect addressing, Based addressing, Indexed
addressing, Based indexed addressing, string addressing
• Group3:
– Direct I/O port addressing, Indirect I/O port addressing
• Group4:
– Relative addressing
• Group5:
– Implied addressing

• Register addressing
– In register addressing the instruction will specify the name of the register
which holds the data to be operated by the instruction
• Ex: a) MOV CL,DH (CL)  (DH)
– The content of 8-bit register DH is moved to another 8-bit register CL
• b) MOV BX,DX (BX)(DX)
• Immediate addressing
– In immediate addressing mode an 8-bit or 16-bit data is specified as part of
the instruction.
• Ex:a) MOV DL,08H (DL)08H
• b) MOV AX,0A9FH (AX)0A9FH

• Direct addressing
– In direct addressing an unsigned 16-bit displacement of signed 8-bit
displacement will be specified in the instruction.
– The displacement is the effective address(EA) or offset.
– The 20 bit physical address of memory is calculated by multiplying the
content of DS register by 10H and adding to effective address.
– In case of 8-bit displacement, the effective address is obtained by sign
extending the 8-bit displacement to 16-bit.
• Examples:
– MOV DX,[08H]
– EA = 0008H (Sign extended 8-bit displacement)
– BA=(DS) * 1610 ; MA=BA+EA
– (DX)  (MA) or DL (MA); DH(MA+1)
• The segment base address (BA) is computed by multiplying the content of DS by 1610
• The memory address (MA) is computed by adding the effective address (EA) to the
segment base address (BA)
• Register Indirect addressing

– In register indirect adddressing the name of the register which holds the
effective address(EA)will be specified in the instruction
– The register used to hold the EA are BX, SI and DI.
– The content of DS is used for segment base address calculation

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CSE-221 Microprocessor and Interfacing

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

• December 23, 1947, John Bardeen, William

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

Intel 4004 1969 108 KH z 2300

Intel 8008 1972 800 KH z 3500

Intel 8080 1974 2 MH z 4500

Intel 8085 1976 3-5MHz 6500

Intel 8086 1978 4.47 MH z 29000

Intel 8088 1981 4.47 MH z 29000

Intel 286 1982 12 MH z 134000

Intel 386 1985 16 MH z 275000

Intel 486 1989 25 MH z 1,200,000

Intel Pentium 1993 66 MH z :3,300,000

Intel Pentium pro 1995 200 MH z 5,500,000

Intel Pentium || 1997 300 MH z 7,500,000

Intel Pentium ||| 1999 500 MH z 9,500,000

Intel Pentium 4 2000 1 GH z 15,500,000

Intel Pentium D 2005 3.6 GH z 47,500,000

Intel Core 2 / Quad 2006 3.6 GH z 214,500,000

SCSE VIT UNIVERSITY A place to learn; A chance to grow

• The worlds first PC ran on an Intel 8088

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

– General Purpose registers can be used to store 8-bit

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

DS BX,SI,DI, 8-or 16-bit

ES DI for string instruction

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

• The minimum mode is selected by applying logic 1 to

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow

SCSE VIT UNIVERSITY A place to learn; A chance to grow