Documente Academic
Documente Profesional
Documente Cultură
Dr.C.Sheeba Joice
Professor & Deputy Head/ECE
Saveetha Engineering College
Chennai – 602 105
CONTENTS
• Introduction – Interfacing
• 8255 – Programmable Peripheral Interface
• 8259 – Programmable Interrupt Controller
• 8254 – Programmable Counter/Interval
Timer
• 8237 – Programmable DMA Controller
Introduction
8255 - Programmable
Peripheral Interface (PPI)
Block
Diagram
of 8255
PIN CONFIGURATION OF 8255
Selection of 8255 ports using address lines.
Programming the 8255
• Three basic modes of operation
– Mode 0 (Basic I/O): three simple I/O ports.
• Ports A and B operate as either inputs or outputs.
• Port C is divided into two 4-bit groups either of which
can be operated as inputs or outputs.
– Mode 1 (Strobed I/O): two hand shaking I/O
ports.
• Ports A and B operate as either inputs or outputs as in
mode 0
• Port C is used for handshaking and control.
– Mode 2 (Strobed Bidirectional I/O): a
bidirectional I/O port with five hand shaking
signals.
• Port A is bidirectional (both input and output).
• Port C is used for handshaking.
• Port B is not used.
Control
Word
Format of
8255
Programming the 8255
• Write the 80x86 initialization routine
required to program the 8255,for mode 0,
with port A as an output and ports B and C
inputs
– The control word is formed as:
• 1 00 0 1 0 1 1 = 8BH
– The program is as follows:
• MOV AL,8BH ;Control byte to AL
• OUT 6,AL ;Write to control port
Programming the 8255
• Write an 80x86 program to input a byte
from port B of the PPI chip in pervious
example and output this byte to port A of
the same chip. Assume the chip has been
programmed as in the previous example.
Bus
RD Read/
WR Write IR0
Interrupt
A0 Logic IN Priority Request IR1
Service Resolver Register
CS Register IRR
ISR
CAS0 IR7
Cascade
CAS1 Buffer/
CAS2 Comparator
Interrupt Mask Register
SP / EN IMR
Internal Bus
INTERRUPT OPERATION
• EI
• Control Words in the Control Register – To initialize
8259
• 2 Types of Control Words:
1. Initialization Command Words (ICWs)
2. Operational command Words (OCWs)
INTERRUPT OPERATION
• IRR stores the requests
• PR examines IRR,IMR,ISR
• INTA from MPU
• Appropriate bit in ISR is SET & corresponding bit in IRR
is RESET
• Opcode for CALL placed in data bus
• Decodes CALL & sends 2 INTA signals
• CALL address – Vector memory location – placed in
Control register during initialization
• ISR bit RESET – (1) AEOI (2) EOI (by ICW)
Operating Modes of 8259
Priority Modes
• Automatic EOI
Additional Features
• Interrupt Triggering
• Interrupt Status
• Poll Method
Programming 8259A
Initialization Command Words ICW1 and ICW2
A0 D7 D6 D5 D4 D3 D2 D1 D0
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 M7 M6 M5 M4 M3 M2 M1 M0
1 – Mask Set
0 – Mask Reset
OCW1
A0 D7 D6 D5 D4 D3 D2 D1 D0
OCW3
1 – Poll 0 0 No Action
No Action 0 0 Command 0 1
0 1 0 – No Poll Read IRR on next
Reset Special 1 0
1 0 Command RD pulse
Mask 1 1
Set Special 1 1 Read IRR on next
Mask RD pulse
Operation Command Word
OCW2
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 R SL EOI 0 0 L2 L1 L0
0 1 2 3 4 5 6 7
0 1 0 0 0 1 0 1
0 0 1 1 0 0 1 1
0 0 0 0 1 1 1 1
END OF
INTERRUPT 0 0 1 NON-SPECIFIC EOI COMMAND
0 1 1 SPECIFIC EOI COMMAND
1 0 1 ROTATE ON NON-SPECIFIC EOI MODE (SET)
AUTOMATIC
1 0 0 ROTATE IN AUTOMATIC EOI MODE (SET)
ROTATION 0 0 0 ROTATE IN AUTOMATIC EOI (CLEAR)
SPECIFIC 1 1 1 ROTATE ON SPECIFIC EOI COMMAND
ROTATION 1 1 0 SET PRIORITY COMMAND*
0 1 0 NO OPERATION
* - In this Mode L0 – L2 are used
Two cascaded PICs
8253
Programmable Interval
Timer/Counter
Applications
• Real time clock
• Event Counter
• Digital One shot
• Square wave generator
• Complex wave form generator
Pin Configuration
Block Diagram
Internal 8254 Registers
RD WR A0 A1 Function
1 0 0 0 Load counter 0
COUNTER 0
0 1 0 0 Read counter 0
1 0 0 1 Load counter 1
COUNTER 1
0 1 0 1 Read counter 1
1 0 1 0 Load counter 2
COUNTER 2
0 1 1 0 Read counter 2
MODE WORD or
1 0 1 1 Write mode word
CONTROL WORD
-- 0 1 1 1 No-operation
Control Word Format
D7 D6 D5 D4 D3 D2 D1 D0
SC – Select Counter
SC1 SC0
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Illegal
RL – Read/Load
RL1 RL0
0 0 Counter Latching operation
1 0 Read / Load most significant byte only
0 1 Read / Load least significant byte only
1 1 Read / Load least significant byte first, then MSB
Read Operations:
• Inhibition
• Reading on the fly
Gate Settings of a Counter
Signal
Status Low or going low Rising High
Mode
Enables
0 Disables counting --
counting
1
1) Initiates counting
-- --
2) Resets output after next clock
1) Disables counting
2 1) Reloads counter Enables
2) Sets output
2) Initiates counting counting
immediately high
1) Disables counting
Enables
3 2) Sets output Initiates counting
counting
immediately high
Enables
4 Disables counting --
counting
5 -- Initiates counting --
Mode Description
D3 D2 D1
Mode value
M2 M1 M0
• BURST mode
– Sometimes called Block Transfer Mode.
– An entire block of data is transferred in one contiguous
sequence. Once the DMA controller is granted access to the
system buses by the CPU, it transfers all bytes of data in the
data block before releasing control of the system buses back to
the CPU.
– This mode is useful for loading programs or data files into
memory, but it does render the CPU inactive for relatively long
periods of time.
CYCLE STEALING Mode
• Advantages of DMA
– Computer system performance is improved by direct
transfer of data between memory and I/O devices,
bypassing the CPU.
– CPU is free to perform operations that do not use
system buses.
• Disadvantages of DMA
– In case of Burst Mode data transfer, the CPU is
rendered inactive for relatively long periods of time.
Thank You