“8086 Interrupts”

Lecture-15

M. M. Yasin
myasin@ciitsahiwal.edu.pk

Fall 2015 - M. M. Yasin 1.1

 “8086 Interrupts”
Introduction
An interrupt is the method of processing the
microprocessor by a peripheral device. It is used to cause a
temporary halt in the execution of a program.
Microprocessor responds to the interrupt with an
interrupt service routine, which is a short program or
subroutine that instructs the microprocessor on how to
handle the interrupt.
There are two basic type of interrupts:
(1) Non-Maskable: It requires an immediate response by
microprocessor, usually used for serious circumstances like
power failure.
(2) Maskable: Microprocessor can ignore it depending upon
some predetermined conditions.

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 “8086 Interrupts”

Interrupt can be divided into five groups:

1. Hardware interrupt

2. Non-Maskable interrupt

3. Software interrupt

4. Internal interrupt

5. Reset

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 “8086 Interrupts”
Hardware, Software and Internal interrupts are serviced on
priority basis.
Each interrupt is given a different priority level by assigning it
a type number. Type 0 identifies the highest-priority and type
255 identifies the lowest- priority interrupt.

The 80x86 chips allow up to 256 vectored interrupts. This

means that you can have up to 256 different sources for an
interrupt and the 80x86 will directly call the service routine
for that interrupt without any software processing.
(This is in contrast to non-vectored interrupts that transfer control directly
to a single interrupt service routine, regardless of the interrupt source).

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 “8086 Interrupts”
Interrupt Vector Table Details
The 80x86 provides a 256 entry interrupt vector table
beginning at address 0:0 in memory. This is a 1K table
containing 256 4-byte entries.
Each entry in this table contains a segmented address that
points at the interrupt service routine in memory.

Int 0  4: Dedicated to specific interrupts, details in the next

slide.
Int 5  31: Reserved by Intel for use in future
microprocessors.
Int 32  255: Available to use for hardware and software
interrupts.

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 “8086 Interrupts”
Details of INT 0  4
INT 0: Known as divide by zero interrupt. For cases where the
quotient becomes particularly large to be placed.
INT 1: Known as single step interrupt. This type of interrupt is
primarily used for debugging purposes in assembly language.
INT 2: Also known as Non-Maskable NMI interrupt. These
type of interrupts are used for emergency scenarios such as
power failure.
INT 3: Breakpoint interrupts. When this interrupt occurs, a
program would execute up to its break point.
INT 4: Also known as overflow interrupt, is generally existent
after an arithmetic operation was performed.

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 “8086 Interrupts”
What happens when an Interrupt occurs
When an interrupt occurs, regardless of the source, the 80x86
does the following:
1. The CPU pushes the flags register onto the stack.
2. The CPU pushes a far return address (segment:offset) onto
the stack, segment value first.
3. The CPU determines the cause of the interrupt (i.e., the
interrupt number) and fetches the four byte interrupt vector
from address 0:vector*4.
– The interrupt type N is sent to the Central Processor Unit (CPU) via
the Data bus from the hardware interface.
– The interrupt vector contents are fetched, from (4 x N) and then
placed into the IP and from (4 x N +2) into the CS.

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 “8086 Interrupts”
4. The CPU transfers control to the routine specified by the
interrupt vector table entry.

What happens when an Interrupt Service Routine finishes…

When the interrupt service routine wants to return control, it

must execute an IRET (interrupt return) instruction. The
interrupt return pops the return address and the flags off the
stack.

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 “8086 Interrupts”
Hardware Interrupt
The primary sources of interrupts are the PCs timer chip,
keyboard, serial ports, parallel ports, disk drives, CMOS real-
time clock, mouse, sound cards, and other peripheral devices.

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt pin
(NMI) which has higher priority than the maskable interrupt
request pin (INTR). A typical use would be to activate a power
failure routine.

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 “8086 Interrupts”
Maskable Interrupt
Whenever an external signal activates the INTR pin, the
microprocessor will be interrupted only if interrupts are
enabled using set interrupt Flag instruction.

If the interrupts are disabled using clear interrupt Flag

instruction, the microprocessor will not get interrupted even
if INTR is activated. That is, INTR can be masked.

INTR is a non vectored interrupt, which means, the 8086 does

not know where to branch to service the interrupt. The 8086
has to be told by an external device like a Programmable
Interrupt controller regarding the branch.

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 “8086 Interrupts”
Software Interrupt Instructions
There are instructions in 8086 which cause an interrupt.
They are INT instructions with type number specified.
For example, INT 3 instruction. It’s a Break Point Interrupt
instruction.

When a break point is inserted, the system executes the

instructions up to the breakpoint, and then goes to the break
point procedure.
Unlike the single-Step feature which stops execution after
each instruction, the breakpoint feature executes all the
instructions up to the inserted breakpoint and then stops
execution.

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 “8086 Interrupts”
Reset
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin.
The 8086 RESET is required to be HIGH for greater than 4 CLK
cycles.
The 8086 will terminate operations on the high-going edge of
RESET and will remain inactive as long as RESET is HIGH.
The low-going transition of RESET triggers an internal reset
sequence for approximately 10 CLK cycles. After this interval
the 8086 operates normally beginning with the instruction in
absolute location FFFF0H.

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 “8086 Interrupts”
Reset

Table: Process initialization register content

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