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http://www.comp.nus.edu.sg/~cs1104
J Q0 J Q1
CLK C C
Q0
K K
FF0 FF1
CLK 1 2 3 4
Q0 Timing diagram
Q0 0 1 0 1 0 00 01 10 11 00 ...
Q1 0 0 1 1 0
J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2
CLK 1 2 3 4 5 6 7 8
Q0 0 1 0 1 0 1 0 1 0
Q1 0 0 1 1 0 0 1 1 0
Q2 0 0 0 0 1 1 1 1 0
Recycles back to 0
CLK 1 2 3 4
Q0
Q1
Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)
CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0
Q1
Q2
Q3
1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by
clearing (a MOD-8
B
binary counter)
C when count of six
NAND 1 (110) occurs.
Output 0
111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.
101 011
100
Q K Q K Q K Q K Q K Q K
CLR CLR CLR CLR CLR CLR
C
D
E All J = K = 1.
F
HIGH
D C B A
J Q J Q J Q J Q
CLK C C C C
K K K K
CLR CLR CLR CLR
1 2 3 4 5 6 7 8 9 10 11
Clock
D 0 1 0 1 0 1 0 1 0 1 0
C 0 0 1 1 0 0 1 1 0 0 0
B 0 0 0 0 1 1 1 1 0 0 0
A 0 0 0 0 0 0 0 0 1 1 0
NAND
output
1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C down counter
Q' K Q' K Q'
K
CLK 1 2 3 4 5 6 7 8
Q0 0 1 0 1 0 1 0 1 0
Q1 0 1 1 0 0 1 1 0 0
Q2 0 1 1 1 1 0 0 0 0
Q0 Q1 Q2 Q3 Q4
J Q J Q J Q J Q J Q
CLK C C C C C
Q' K Q' Q' K Q' K Q'
K K
A5 A4 A3 A2 A1 A0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
: : : : : :
CS1104-13 Cascading Asynchronous 21
Counters
Cascading Asynchronous Counters
If counter is a not a binary counter, requires
additional output.
Example: A modulus-100 counter using two decade
counters.
freq/10
1 CTEN Decade CTEN Decade freq/100
counter TC counter TC
CLK C Q3 Q2 Q1 Q0 C Q3 Q2 Q1 Q0
freq
A0 J A1
J Q Q
C C
Q' K Q'
K
CLK
1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1
A0 A0 A0
TA2 = A1.A0 TA1 = A0 TA0 = 1
CS1104-13 Synchronous (Parallel) Counters 25
Synchronous (Parallel) Counters
Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1
A2 A1 A0
Q Q Q
J K J K J K
CP
1
1 A1.A0 A2.A1.A0
A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K
CLK
Q0
1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'
CLK
Q0 Q1
1 T T T Q2
Q Q Q
Up C C C
Q' Q' Q'
CLK
Q0 Q1 Q2
J Q J Q J Q
C C C
Q1 Q2
K Q' K Q' ' K Q' '
Q0
'
CLK
A4 A3 A2 A1 A4 A3 A2 A1
Carry-out
Count = 1 Count = 1
Load
Clear = 1 Clear = 1
Load
I4 I3 I2 I1 CP I4 I3 I2 I1 CP
1 0 1 0 0 0 1 1
(c) Binary states 10,11,12,13,14,15. (d) Binary states 3,4,5,6,7,8.
CS1104-13 Counters with Parallel Load 41
Counters with Parallel Load
4-bit counter with
parallel load.
Clear CP Load Count Function
0 X X X Clear to 0
1 X 0 0 No change
1 1 X Load inputs
1 0 1 Next state
Q Q Q Q
D D D D
CP
I3 I2 I1 I0
D Q A1
I1
D Q A2
I2
D Q A3
I3
CLK
CLEAR
Register Combin-
Clock ational
circuit
Inputs Outputs
Present Next
state Input State Output
A1 A2 x A1+ A2+ y
0 0 0 0 0 0 A1.x' A
0 0 1 0 1 0 1
0 1 0 0 1 0 A2x A2
0 1 1 0 0 1
1 0 0 1 0 0
x y
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 0 0 1
Address Outputs
1 2 3 1 2 3
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0 A1
0 1 1 0 0 1 A2 8x3
1 0 0 1 0 0 ROM
1 0 1 0 1 0 x y
1 1 0 1 1 0
1 1 1 0 0 1
(a) Serial in/shift right/serial out (b) Serial in/shift left/serial out
Data in Data in
Data in
Data out
Data out
(c) Parallel in/serial out (d) Serial in/parallel out
Data out
(e) Parallel in /
parallel out
CLK
SI SO SI SO
Shift register A Shift register B
Clock CP
Shift control
Clock
Shift Wordtime
control
CP
T1 T2 T3 T4
CLK
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
D0 D1 D2 D3
SHIFT/LOAD
Serial
D Q D Q D Q D Q data
Q0 Q1 Q2 Q3 out
C C C C
CLK
SHIFT.Q0 + SHIFT'.D1
Data in
D0 D1 D2 D3
SHIFT/LOAD SRG 4
Serial data out
CLK C
Logic symbol
D0 D1 D2 D3
D Q D Q D Q D Q
C C C C
CLK
Q0 Q1 Q2 Q3
RIGHT/LEFT
Serial
data in
RIGHT.Q0 + D Q D Q D Q D Q Q3
RIGHT'.Q2 Q1 Q2
C C C C
Q0
CLK
A4 A3 A2 A1
Q Q Q Q
Clear
D D D D
CLK
Serial
input for Serial
shift-right input for
I4 I3 I2 I1 shift-left
Parallel inputs
CS1104-13 Bidirectional Shift Registers 60
Bidirectional Shift Registers
4-bit bidirectional shift register with parallel load.
Mode Control
s1 s0 Register Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
Clear
CS1104-13 An Application – Serial Addition 62
An Application – Serial Addition
A = 0100; B = 0111. A + B = 1011 is stored in A
after 4 clock pulses.
Initial: A: 0 1 0 0 Q: 0
B: 0 1 1 1
Step 1: 0 + 1 + 0 A: 1 0 1 0 Q: 0
S = 1, C = 0 B: x 0 1 1
Step 2: 0 + 1 + 0 A: 1 1 0 1 Q: 0
S = 1, C = 0 B: x x 0 1
Step 3: 1 + 1 + 0 A: 0 1 1 0 Q: 1
S = 0, C = 1 B: x x x 0
Step 4: 0 + 0 + 1 A: 1 0 1 1 Q: 0
S = 1, C = 0 B: x x x x
CLR
CLK
Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100
Clock Q0 Q1 Q2 Q3 0000
0 0 0 0 0
0001 1000
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0 0011 1100
4 1 1 1 1
5 0 1 1 1 0111 1110
6 0 0 1 1
7 0 0 0 1 1111
k Memory unit
k address lines
2k words
n bits per word
Read/Write
n data
output lines
Memory address
binary decimal Memory content
0000000000 0 1011010111011101
0000000001 1 1010000110000110
0000000010 2 0010011101110001
: : :
: : :
1111111101 1021 1110010101010010
1111111110 1022 0011111010101110
1111111111 1023 1011000110010101
Select
Select
R
Read/Write
Read/Write
RAM 1K x 8
S0 0 1024 – 2047
1 DATA (8) (8)
S1 2 ADRS (10)
3 CS
1K x 8
RW
2048 – 3071
Read/write DATA (8) (8)
ADRS (10)
CS
1K x 8
RW
3072 – 4095
DATA (8)
4K x 8 RAM. ADRS (10)
CS
(8)
1K x 8 Output
RW
data
CS1104-13 Random Access Memory (RAM) 78
End of segment