MPMC

8086 Microprocessor
UNIT–I:
 Introduction to Microprocessor Architecture:

 Introduction and evolution of Microprocessors Architecture of 8086
 Register Organization of 8086
 Memory organization of 8086
 General bus operation of 8086
 Introduction to 80286
 80386 and 80486 and Pentium.
2
Microprocessor
Program controlled semiconductor device (IC)

which fetches (from memory), decodes and executes
instructions.
It is used as CPU (Central Processing Unit) in

computers.
3
Microprocessor Fifth Generation Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology  Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 4
multiplexed Intel 8085 (8 bit processor)
 Intel 4004
 Intel 8008
 Intel 8080
 Intel 8085
 1ntel 8086
 1ntel 80286
 Intel 80386
 Intel 80486
 Intel Pentium
 Intel Pentium-ii
 Intel Pentium-iii
 Intel Pentium-iv
 Intel Pentium -D
 Intel Pentium core
 Intel core 2
5
Intel 4004
Maximum CPU clock rate:740KHZ
Minimum feature size : 10 micro meters
Instruction set: 4bit BCD
Transistors: 2,300
6
Intel 8008:
 byte oriented microprocessor
 1st chip on 1972
 Max clock: 0.2MHZ to 0.8 MHz
 Size: 10 micrometers
7
 Zilog
 Fairchild
 Motorolla
8
9
10
Microprocessor Functional blocks
Various conditions of the

Computational Unit;
results are stored as
performs arithmetic and Internal storage of data
status bits called flags in
logic operations
flag register
Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP
Control Bus Address Bus
Generates control signals for

internal and external Decodes instructions; sends
operations of the information to the timing and
control unit 11
microprocessor
 Introduction to Microprocessor Architecture:
 Introduction and evolution of Microprocessors Architecture of

8086
 Register Organization of 8086
 Memory organization of 8086
 General bus operation of 8086
 Introduction to 80286
 80386 and 80486 and Pentium.
12
8086 Microprocessor
Overview
First 16- bit processor released by Addressable memory space is

INTEL in the year 1978 organized in to two banks of 512 kb
each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to
Originally HMOS, now manufactured select even bank and control signal 𝐁𝐇𝐄
using HMOS III technique is used to access odd bank
Uses a separate 16 bit address for I/O

Approximately 29, 000 transistors, 40 mapped devices  can generate 216 =
pin DIP, 5V supply 64 k addresses.
Operates in two modes: minimum mode

Does not have internal clock; external and maximum mode, decided by the
asymmetric clock source with 33% signal at MN and 𝐌𝐗 pins.
duty cycle
20-bit address to access memory  can

address up to 220 = 1 megabytes of
memory space.
13
Pins and signals
8086 Microprocessor
Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are

multiplexed with data.
When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are

multiplexed with status signals
15
8086 Microprocessor
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the

processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.

It is an output signal.
It is active when low.
16
8086 Microprocessor
TEST
𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’

instruction.
8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.
This is used to synchronize an external

activity to the processor internal
operation.
READY
This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.
The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high. 17

8086 Microprocessor
RESET (Input)
Causes the processor to immediately

terminate its present activity.
The signal must be active HIGH for at

least four clock cycles.
CLK
The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.
This signal is active high and internally

synchronized. 18
19
8086 Microprocessor
Pins and Signals Min/ Max Pins
The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.
In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.
Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.
20
8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)
8086 itself generates all the bus control signals
DT/𝐑
ഥ (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
𝐃𝐄𝐍 (Data Enable) Output signal from the processor

used as out put enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
M/𝐈𝐎 Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.
𝐖𝐑 Write control signal; asserted low Whenever

processor writes data to memory or I/O port
𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
21
8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)
8086 itself generates all the bus control signals
HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.
Usually used by the DMA controller to get the

control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.
The acknowledge is asserted high, when the

processor accepts HOLD.
22
8086 Microprocessor
Pins and Signals Maximum mode signals
During maximum mode operation, the MN/ 𝐌𝐗 is

grounded (logic low)
Pins 24 -31 are reassigned
𝑺𝟎 , 𝑺𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.
23
8086 Microprocessor

𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the status

of queue in these lines.
The queue status can be used by external device to

track the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted as

shown in the table.
24
8086 Microprocessor

𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are used

𝐑𝐐/𝐆𝐓𝟏 by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.
These pins are bidirectional.
The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏
𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix

instruction.
Remains active until the completion of the

instruction prefixed by LOCK.
The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.
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Architecture
27
8086 Microprocessor
Architecture
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
28
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Dedicated Adder to generate

20 bit address
Four 16-bit segment

registers
Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >> 29

8086 Microprocessor
Segment
Registers
8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.
30
8086 Microprocessor
Segment Code Segment Register

Registers
16-bit
CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset
is added provided by the IP.
31
8086 Microprocessor
Segment Data Segment Register

Registers
16-bit
Points to the current data segment; operands for most

instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.
32
8086 Microprocessor
Segment Stack Segment Register

Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).
33
8086 Microprocessor
Segment Extra Segment Register

Registers
16-bit
Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine the 20-

bit physical address for the destination.
34
8086 Microprocessor
Segment Instruction Pointer

Registers
16-bit
Always points to the next instruction to be executed within

the currently executing code segment.
So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution

of the next instruction takes place.
35
8086 Microprocessor
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.
This mechanism is known

as pipelining.
36
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
16-bit ALU for

performing arithmetic
and logic operation
Four general purpose

registers(AX, BX, CX, DX);
Pointer registers (Stack

Pointer, Base Pointer);
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 37
DX can be used as DH and DL
8086 Microprocessor
EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,

and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or

AL.
38
8086 Microprocessor
EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.
This is the only general purpose register whose contents

can be used for addressing the 8086 memory.
All memory references utilizing this register content for

addressing use DS as the default segment register.
39
8086 Microprocessor
EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.
Example:
The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.
40
8086 Microprocessor
EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.
Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 ÷ 16 division and the 16-bit reminder after division.
41
8086 Microprocessor
EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.
SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.
42
8086 Microprocessor
EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
43
8086 Microprocessor
EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
44
8086 Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 45
46
8086 Microprocessor
Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register

47
8086 Microprocessor
Architecture Registers and Special Functions
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations
BX Base register Used to hold base value in base addressing mode

to access memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions
DX Data Register Used to hold data for multiplication and division

operations
SP Stack Pointer Used to hold the offset address of top stack

memory
BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory
SI Source Index Used to hold index value of source operand (data)

for string instructions
DI Data Index Used to hold the index value of destination

operand (data) for string operations 48
Interfacing memory and i/o ports
8086 Microprocessor
Memory
Processor Memory
 Registers inside a microcomputer
 Store data and results temporarily
 No speed disparity
 Cost 
Primary or Main Memory

 Storage area which can be directly
Memory accessed by microprocessor
 Store programs and data prior to
Store
execution
Programs
 Should not have speed disparity with
and Data
processor  Semi Conductor
memories using CMOS technology
 ROM, EPROM, Static RAM, DRAM
Secondary Memory
 Storage media comprising of slow
devices such as magnetic tapes and
disks
 Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 50
8086 Microprocessor
Memory organization in 8086
Memory IC’s : Byte oriented
8086 : 16-bit
Word : Stored by two

consecutive memory locations;
for LSB and MSB
Address of word : Address of

LSB
Bank 0 : A0 = 0  Even
addressed memory bank
Bank 1 : 𝑩𝑯𝑬 = 0  Odd

addressed memory bank
51
8086 Microprocessor
Operation 𝑩𝑯𝑬 A0 Data Lines Used
1 Read/ Write byte at an even address 1 0 D7 – D0
2 Read/ Write byte at an odd address 0 1 D15 – D8
3 Read/ Write word at an even address 0 0 D15 – D0
4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation

byte from odd bank is
transferred
1 0 D7 – D0 in first operation
byte from odd bank is
transferred 52
8086 Microprocessor
 Available memory space = EPROM + RAM
 Allot equal address space in odd and even bank for

both EPROM and RAM
 Can be implemented in two IC’s (one for even and

other for odd) or in multiple IC’s
 FFFF0H to FFFF5H-------initialization process
 FFFF6H to FFFFBH -------8089 initialization process

i/o processor.
 00000H to 00013H-------vector addresses of

dedicated interrupts.
 00000H to 003FFH -------IVT
53
8086 Microprocessor
Interfacing SRAM and EPROM
Memory interface  Read from and write in

to a set of semiconductor memory IC chip
EPROM  Read operations
RAM  Read and Write
In order to perform read/ write operations,
Memory access time  read / write time of

the processor
Chip Select (CS) signal has to be generated
Control signals for read / write operations
Allot address for each memory location
54
8086 Microprocessor
Typical Semiconductor IC Chip
No of Memory capacity Range of

Address address in
pins hexa
In Decimal In kilo In hexa
20 220= 10,48,576 1024 k = 1M 100000 00000

to
FFFFF
55
8086 Microprocessor
Memory map of 8086
EPROM’s are mapped at FFFFFH

 Facilitate automatic execution of monitor programs
and creation of interrupt vector table
RAM are mapped at the beginning; 00000H is allotted to RAM
56
8086 Microprocessor
Monitor Programs
 Programing 8279 for keyboard scanning and display
refreshing
 Programming peripheral IC’s 8259, 8257, 8255,

8251, 8254 etc
 Initialization of stack
 Display a message on display (output)
 Initializing interrupt vector table
Note : 8279 Programmable keyboard/ display controller
8257 DMA controller
8259 Programmable interrupt controller
8255 Programmable peripheral interface
57
8086 Microprocessor
Interfacing I/O and peripheral devices
I/O devices
 For communication between microprocessor and
outside world
 Keyboards, CRT displays, Printers, Compact Discs

etc.

Ports / Buffer IC’s
Microprocessor I/ O devices
(interface circuitry)
 Data transfer types

Memory mapped
Programmed I/ O
Data transfer is accomplished I/O mapped
through an I/O port
controlled by software
Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 58
bypassing the microprocessor
System bus cycle of 8086
59
8086 Microprocessor
8086 and 8088 comparison
Memory mapping I/O mapping

20 bit address are provided for I/O 8-bit or 16-bit addresses are
devices provided for I/O devices
The I/O ports or peripherals can be Only IN and OUT instructions can be
treated like memory locations and used for data transfer between I/O
so all instructions related to device and processor
memory can be used for data
transmission between I/O device
and processor
Data can be moved from any Data transfer takes place only
register to ports and vice versa between accumulator and ports
When memory mapping is used for Full memory space can be used for
I/O devices, full memory address addressing memory.
space cannot be used for
addressing memory.  Suitable for systems which
require large memory capacity
 Useful only for small systems
where memory requirement is less
For accessing the memory mapped For accessing the I/O mapped
devices, the processor executes devices, the processor executes I/O
memory read or write cycle. read or write cycle.
 M / 𝐈𝐎 is asserted high  M / 𝐈𝐎 is asserted low 60

61
80286 microprocessor
Features of 80286
 The Intel 80286 is a high-performance 16-bit

microprocessor.
 It has been specially designed for multiuser and
multitasking systems.
 Various versions of 80286 are available that run on 12.5
MHz,10 MHz and 8MHz clock frequencies.
 80286 is upwardly compatible with 8086 in terms of
instruction set. (That is the 8086,8088,80186,80286 CPU
family all contain the same instruction set)
Features of 80286
 It has 24 address lines and 16 data lines.

 There are two operating modes for 80286
 The real address mode
 The protected virtual memory address mode
 In real address mode the processor can address up
to 1MB of physical memory.
Features of 80286
The virtual address mode is for

multiuser/multitasking system. In this mode of
operation the memory management unit can
manage up to 1GB of virtual memory.
In virtual address mode one user cannot

interface with the other. Also users cannot
interface with operating system. These features
are called protection. Features of 80286
(Cont.)
Features of 80286
 The 80286 CPU contains almost the same set of registers, as in 8086,
viz.
 (a) Eight 16-bit general purpose registers
 (b) Four 16-bit segment registers
 (c) Status and control register
 (d) Instruction Register
 The flag register bits D0, D2, D4, D6, D7 and D11 are modified
according to the result of the execution of logical and arithmetic
instructions. These are called status flag bits.
Register Set of 80286
FLAG REGISTES
• The additional fields available in 80286 flag
registers are
• IOPL-I/O Privilege Field (bits D12 and D13)
• NT - Nested Task flag (bit D14)
• PE - Protection Enable (bit D16)
• MP – Monitor Processor Extension (bit D17)
• Processor Extension Evaluator (bit D19)
• Machine Status Flag (MSW) :
The machine status word consists of four flags.
These are – PE,MP,EM, and TS of the four lower
order bits D19 to D16 of the upper word of the
flag register.  The LMSW and SMSW instructions
are available in the instruction set of 80286 to
write and read the MSW in real address mode
INTERNAL ARTECTURE OF
80286
80386 microprocessor
Features of 80386
It supports 8/16/32 bit data operands
It has 132 pins.
It has 32-bit internal registers
It supports 32-bit data bus and 32-bit non-

multiplexed address bus.
Features of 80386
 It supports Physical Address of 4GB

 Maximum Segment size of 4GB
 Virtual Address of 64TB(4GB seg. * 16,384 segments)
 3 Types of 80386
 1. 80386DX(floating point capability.)
 2. 80386SX(16-bit data bus)
 3. 80386SL(several power management options)
Features of 80386
 It operates in 3 different modes

 Real
 Protected
 Virtual .
 MMU provides virtual memory, paging and 4 levels of

protection
 Low cost & low power consumption.
 Clock Frequency : 20,25 and 33MHz
Architecture of 80386
Central Processing Unit
Memory Management Unit
Bus Control Unit

Central Processing Unit:
 Architecture of 80386 The CPU is further divided into:

 Execution Unit
 Instruction Unit
 Execution Unit:
 Execution unit has 8 General and Special purpose
registers, which are either used for handling data or
calculating offset addresses.
 The 64-bit barrel shifter increases the speed of all shift,
rotate.
 Multiply/divide logic implements the bit-shift- rotate
algorithms to complete the operation in minimum time.
Instruction Unit:
• It decodes the opcode bytes received from the 16-byte instruction

code queue and arrange them into a 3- decoded instruction queue.
• After decoding it is passed to control section for deriving
necessary control signals
Memory Management Unit
Paging Unit:
 It organizes physical memory in terms of pages of 4KB
size.
 It works under the control of segmentation unit i.e.
each segment is divided into pages.
 It converts linear addresses into physical addresses.
 The control and attribute PLA checks privileges at
page level.
Bus Control Unit:
It has a prioritizer to resolve the priority

of various bus requests. This controls the
access of the bus.
 The address driver drives the bus enable

and address signals A2 – A31.
Flag registers:
Register set of 80386:
80486MICROPROCESS
OR AND
PENTIUM
91
92
INTRODUCTION OF 80486
• The Intel80486 Is Also Known As I486 0r 486.

• Introduced In 1989.
• 486 Is An Improved Version Of 80386 Which Contains 8k
Of Cache.
• It Executes Many Instructions Only In One Clock Cycle.
93
• 168PINS
• 32 ADDRESS PINS
• 32 DATA PINS
• Data Bus Width: 32 bit
• Address bus : 32 bit
• Memory Size: 4G +16K cache
94
NEED OF 80486 OVER 80386
95
PIN DIAGRAM
96
CLK2 ADDRESS
2X CLOCK A2 – A31
BUS
BE3#
32 BIT
DATA D – D DATA BE2#
0 31 32 – BIT
BUS ADDRESS
BE1# BYTE BUS
ADS#
ENABLINES
BE0#
BUS RDY#
CONTROL
W/R#
INTR
D / C#
NMI
INTERRUPTS M / IO BUS CYCLE

RESET DEFINATION
LOCK#
80486 PROCESSOR
AHOLD PLOCK#
CACHE EADS HOLD

INVALIDATION #
HLDA BUS
KEN# BOFF# ARBITRATION
CACHE
CONTROL FLUSH# BREQ
PWT BRDY#
PAGE BLAST BUS CONTROL
CACHING #
CONTROL PCD
BS8#
BUS SIZE
BS16# CONTROL
FERR#
NUMERIC DP3
ERROR IGNNE DP2
REPORTING DP1
DP0 PARITY
ADDRESS BIT A20M#
20 MASK PCHK#
97
FEATURES OF 80486
• It Has 1kb Of Cache.

• Integrated FPU(floating Point Unit).
• Improved MMU.
– Memory Segment And Paging Are Supported
– Address Management And Memory Space Protection.
98
• TIGHTELY COUPLED PIPELINING
– FETCHING,DECODING,ADDRESS TRANSULATION
OVERLAPED
– SINGLE CYCLE EXECUTION
A 5OMHZ 80486 EXECUTES AROUND 40MILLION

INSTRUCTIONS IN JUST ONE SEC.
99
100
REGISTERS
GENERAL PURPOSE REGISTERS

31 16 15 0
AX EAX
BX EBX
CX ECX
DX EDX
SI ESI
DI EDI
BP EBP
SP ESP
SEGMENT REGISTERS
CODE SEGMENT
CS
STACK SEGMENT
SS
DS
ES
DATA SEGMENT
FS
GS
INSTRUCTION POINTER AND FLAG REGISTER

31 16 15 0
IP EIP
FLAGS EFLAGS
101
Flag Register of 80486
FLAGS
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E
F RESERVED FOR
L INTEL AC VM RF 0 NT IOPL OF DF IF TF SF ZF 0 AF 0 PF 1 CF
A
G
CF: Carry Flag

AF: Auxiliary carry
OF : Over Flow
ZF: Zero Flag
IOPL : I/O Privilege Level
SF : Sign Flag
NT : Nested Task Flag
TF : Trap Flag RF : Resume Flag
IE : Interrupt Enable VM : Virtual Mode
AC : Alignment Check
DF : Direct Flag
102
PENTIUM PROCESSOR
103
INTRODUCTION TO PENTIUM
• A 32-bit microprocessor introduced by Intel in 1993.

• It contains 3.3million transistors, nearly triple the
number contained in its predecessor, the 80486 chip.
• Though still in production, the Pentium processor has
been superseded by the Pentium Pro and Pentium II
microprocessors.
104
Contd..
• Since 1993, Intel has developed the Pentium III and

Pentium 4 microprocessors. Recently i7 and i9.
• 60MHZS
105
106
FEATURES OF PENTIUM
• • Introduced in 1993 with clock frequency

ranging from 60 to 66 MHz
• • The primary changes in Pentium Processor
were:
• – Superscalar Architecture
• – Pipelined Floating-Point Unit
• – Separate 8K Code and Data Caches
• – Write back MESI Protocol in the Data Cache
• – 64-Bit Data Bus
• – Bus Cycle Pipelining
107
• Added second execution pipeline
– Superscalar performance
– Two instructions/clock
• Added branch prediction
108
109
PIN DIAGRAM
110
ARCHITECTURE
111
PENTIUM ARCHITECTURE
• • It has data bus of 64 bit and address bus of 32-bit

• • There are two separate 8kB caches – one for
code
• and one for data.
• • Each cache has a separate address translation TLB
• which translates linear addresses to physical.
112
• Instruction Decode Unit:
• • It occurs in two stages – Decode1 (D1) and
Decode2(D2)
• • D1 checks whether instructions can be
paired
• • D2 calculates the address of memory
resident operands
• Prefetch Buffers:
• Four prefetch buffers within the processor works as
two
independent pairs. calculates the address of
memory resident operands
113
REGISTERS
114
115
116

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8086 Microprocessor

 Introduction to Microprocessor Architecture:

Program controlled semiconductor device (IC)

It is used as CPU (Central Processing Unit) in

Maximum CPU clock rate:740KHZ

Minimum feature size : 10 micro meters

Instruction set: 4bit BCD

 byte oriented microprocessor

 1st chip on 1972

 Max clock: 0.2MHZ to 0.8 MHz

Various conditions of the

Register array or Data Bus

Control Bus Address Bus

Generates control signals for

 Introduction and evolution of Microprocessors Architecture of

 Register Organization of 8086

 Memory organization of 8086

 General bus operation of 8086

 80386 and 80486 and Pentium.

First 16- bit processor released by Addressable memory space is

Uses a separate 16 bit address for I/O

Operates in two modes: minimum mode

20-bit address to access memory  can

Low order address bus; these are

When AD lines are used to transmit

When data are transmitted over AD lines

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

This pin signal indicates what mode the

RD (Read) (Active Low)

The signal is used for read operation.

𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’

8086 will enter a wait state after

This is used to synchronize an external

This is the acknowledgement from the

The signal made available by the devices

The signal is active high. 17

Causes the processor to immediately

The signal must be active HIGH for at

The clock input provides the basic timing

INTR Interrupt Request

This is a triggered input. This is sampled

This signal is active high and internally

The 8086 microprocessor can work in two

In the minimum mode of operation the

In the maximum mode the 8086 can work

Minimum or maximum mode operations

When this pin is high 8086 operates in

For minimum mode operation, the MN/ 𝐌𝐗 is tied

8086 itself generates all the bus control signals

𝐃𝐄𝐍 (Data Enable) Output signal from the processor

ALE (Address Latch Enable) Used to demultiplex the

M/𝐈𝐎 Used to differentiate memory access and I/O

𝐖𝐑 Write control signal; asserted low Whenever

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

For minimum mode operation, the MN/ 𝐌𝐗 is tied

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

Usually used by the DMA controller to get the

HLDA (Hold Acknowledge) Acknowledge signal by the