1)8051:Micro controller(Detailed

study )->17.1 to 17.10

2)8254/8253:Peripheral Chips for

timing control->6.1
• MODULE 5 second half:
1) 8051 Architecture,
2)Register Organization
3) Memory and I/O addressing
4)Interrupts and Stack
17.1 to 17.10
• MODULE 6
1)8051 Addressing Modes
2)Different types of instructions and Instruction Set
3)Simple programs
4)8253/8254:peripheral chip for timing control 6.1
Architecture of 8051
 1) 8051 Architecture
• What is a micro controller-the device which
contains a microprocessor along with I/O
ports ,memory and programmable timer
• It will make the device a self sufficient one
• Also called single chip microcomputer
• Advantages of Microcontrollers:
 As the peripherals are integrated into a single chip the overall system cost
is very low
 The size of the product is small as compared to the microprocessor based
systems thus very handy
 System design requires very little efforts
 Easy to troubleshoot and maintain
 As the peripherals are integrated with a microprocessor the system is
more reliable
 Though a microcontroller has its own on chip Ram ,ROM and I/O ports
additional RAM,ROM and IO can be integrated
 On-chip ROM provide a software security feature
 All these features available in a 40 pin package
Architecture of 8051
Architecture of 8051
 Architecture of 8051
• Accumulator(ACC or A):
• Acts as an operand register
• It has been allotted an address in the on chip special function
register bank

• B Register:
• This register is used to store one of the operands for multiply
and divide instructions
• Considered as a special function register
 Architecture of 8051
• Program status word(PSW)
• Set of flags contains the status information
• Considered as special function register
• Stack Pointer(SP)
• This register is incremented before the data is stored on
to the stack
• Contains 8 bit stack top address
• After a reset the SP register is initialised to 07
• If sp contains 07 H the next PUSH operation will store
data at address 08H
• The SP content incremented to 08H
 Architecture of 8051
• DATA POINTER
• 16 register (higher byte DPH and lower byte DPL)
• It contains a higher byte and lower byte of a 16 bit external
data RAM address
• Port 0 to 3 Latches and drivers
• Four latches and drivers pair are allocated to each of four on-
chip I/O ports
• Using this the user can communicate with these
ports(P0,P1,P2,P3)
 Architecture of 8051
• Serial Data Buffer(SBUF)
• Internally contain two registers
1)Transmit Buffer(parallel –in Serial Out)
2)Receive Buffer (Serial l –in paralleOut)
• Timer Registers
• 2 ,16 BIT REGISTERS
• Timer register 0(TL0 and TH0)
• Timer register 1(TL1 and TH1)
• 4 address has been allotted to them which lie in special function registers
 Architecture of 8051
• Control Registers
• These are special function registers
• IP,IE,TMOD,TCON,SCON and PCON
• These registers contain control and status information for
interrupts timers, counters and serial port
• Timing and Control Unit
• This unit derives all necessary timing and control signals
required for the internal operation of the circuit
 Architecture of 8051
• Oscillator
• Generate basic timing clock signal for the operation of the
circuit using crystal oscillator
• Instruction Registers
• This register decodes the opcode of an instruction to be
executed and gives info to the timing and control unit
• to generate necessary signals for the execution of the
instruction
• EPROM and Program Address Register
• On-chip EPROM
• necessary mechanism to internally address it
• RAM and RAM Address register
• Provide internal 128 bytes of RAM and
mechanism to address it
• ALU
• Perform 8 bit arithmetic and logical operations

• SFR Register bank

• Set of special function registers
• Signals
• Vcc,Vss,
• RESET,
• ALE/PROG,
• EA/Vpp(can address external program memory),
• PSEN(program strobe enable:probe to read the
eternal program mem)
• Port 0,1,2,3
• XTAL1,XTAL2:input of the amplifier and output of
amplifier
Register organization
 Register Set

General purpose registers/RAM MEM (Byte addressable

registers):
Special function registers (Bit addressable registers)
Special function registers
Special function registers
General purpose memory
• General purpose registers divided in to four
groups of 8 registers each, called register
banks

• The register bank to be accessed can be

selected using RS1 and RS0 bits of an internal
register called program status word
• Registers A and B used to store operands
• DPH and DPL are higher and lower bytes of 16
bit register DPTR(accessing external data
memory)
• Registers TH0,TH1 and TL0,TL1 form a 16-bit
counter/timer Register
• 4 port latches P0,P1,P2,P3
• SP
• PSW
• IPprogrammed to control interrupt priority
• IEprogrammed to control
interrupts(enable/disable)
• TCONtimer/counter control register
• TMODused for programming the modes of
operation of timers and counters
• SCONserial port mode control register(used
to control the operation of serial port)
• SBUFSerial data buffer for transmit and
receive operations
• PCON power control registers(power down bit and
idle bit) 2 MODES
i)idle mode
 oscillator continues to run ,interrupt serial port and
timer blocks are active
 clock to CPU disabled(cpu status preserved)
 This mode can be terminated with a hardware
interrupt/reset signal
• 2)power down mode
On chip oscillator is stopped
Maintain the content of RAM(redefines all
SFRs)
only way to terminate this mode is hardware
reset
Operational feature-PSW
Memory and I/O addressing
 Memory addressing/ORGANIZATION
8051
• The 8051 microcontroller's memory is divided
into
Program Memory
Data Memory.

Program Memory (ROM) is used for permanent

saving program being executed
Data Memory (RAM) is used for temporarily storing
and keeping intermediate results and variables
Memory addressing/organization 8051
ROM
• PROGRAM MEMORY
• Implemented using EPROM
• it stores only program code which is to executed
• Mem is read only
• Data Memory
• Implemented using RAM
• Read from or written to
Memory addressing/organization 8051
ROM
• PROGRAM MEMORY
• Program memory and data memory both
categorized as on-chip and external memory
• Can address 4 Kbytes on-chip program
mem(0000H-0FFFH)
• Can address 64 Kbytes of external program
mem(0000H- FFFFH)
• overlapped mem space can be distingushed
using PSEN signal
Memory addressing/organization 8051
ROM
Memory addressing/organization 8051
RAM
• DATA MEMEORY
1)External data memory
• 8051 supports 64k bytes of external data
memory (0000H to FFFFH)
• External data memory can be accessed under
the control of register DPTR
• 8051 generates RD and WR during external
data memory accesses
Memory addressing/organization 8051
RAM
2)Internal Data Memory
It consists of two parts
1)RAM block of 128 bytes (00 to 7FH)
-addressed using direct/indirect
addressing mode
2)second is the set of addresses from 80h
to FFH
-only with direct addressing mode
Memory addressing/organization 8051
RAM
• Incase of 8051 version with 256 bytes on-chip
RAM, the map starts from 00H ends at FFH
• The address map of special function registers
80H to FFH overlaps with upper 128 bytes of
RAM
• SFR address space can be only be accessed
using direct addressing
• Upper 128 bytes can be accessed using
indirect addressing mode
Memory addressing/organization 8051
RAM
Memory addressing/organization 8051
RAM
• Lower 128 bytes of RAM(00 to 7F) functionally organized in to
3 sections
Section 1 (32 bytes) (00 to 1Fh)
• Address block from 00 to 1FH
• Again divided into 4 banks of 8-bit registers
i)bank 00
ii)bank 01
iii)bank 10
iv)bank 11
• After reset bank 0 is selected by default but
the actual stack data is stored from 08H
onwards
Memory addressing/organization 8051
RAM
• Section 2(16 bytes)(20 to 2F)

• Bit addressable
• Containing 16*8=128 bites
• Can be accessed by specifying the bit
number directly in the instruction
• OR the bit is mentioned with its position
in the respective register byte
• Eg:20.0 to 20.7
Memory addressing/organization 8051
RAM
• Section 3(30H to 7FH)
• Byte addressable
• Used as a stack memory
 Lower 128 Byte of RAM
• LOWER RAM ORGANIZATION
EXTERNAL I/O INTERFACING
 EXTERNAL I/O INTERFACING
• 8051 has internal ports
• Some complex applications may require
additional I/O devices
• Interfaced as external memory mapped
devices
• Devices are treated as external memory
locations
EXTERNAL I/O INTERFACING
INTERRUPTS AND STACK OF 8051
 INTERRUPTS AND STACK OF 8051
• The 8051 microcontroller can recognize five
different events that cause the main program
to interrupt from the normal execution. These
five sources of interrupts in 8051are:
– Timer 0 overflow interrupt- TF0
– Timer 1 overflow interrupt- TF1
– External hardware interrupt- INT0
– External hardware interrupt- INT1
– Serial communication interrupt- RI/TI
 INTERRUPTS AND STACK OF 8051
– External hardware interrupt- INT0
– External hardware interrupt- INT1
• TCON register specifies the type of external interrupt to the
microcontroller.
• External interrupts can be either edge sensitive or level sensitive
• This depends on bits IT0 and IT1 provided in the Register TCON.
• The flags which generate these type of interrupts are bits IE0 and
IE1.
• When an external interrupt is generated, the flag that generated
the interrupt is cleared by the hardware when the service routine is
vectored to ISR location.
• This happens only if the interrupt was edge-triggered.
• If the interrupt was level-triggered, then the external requesting
source is what controls the requested flag, rather than the on-chip
hardware.
 INTERRUPTS AND STACK OF 8051
– Timer 0 overflow interrupt- TF0
– Timer 1 overflow interrupt- TF1
• Timer-0 & Timer-1 Interrupts are generated by
TF0 and TF1 bits of register TCON.
• When these interrupts are generated
respective flags are automatically cleared after
the control is transferred to respective
interrupt service routine
 INTERRUPTS AND STACK OF 8051
• Serial communication interrupt- RI/TI

• Serial interrupt is generated if at least one of the two

bits RI or TI is set of serial control register SCON.
• Neither of the bit is cleared after the control is
transferred to ISR
• It should be rest by the software
 INTERRUPTS OF 8051
• Interrupt Priorities
• Two level of interrupt priorities
• Using the interrupt Priority Register(IP) we can
set the priority(programmed)
• Interrupts can be set using Interrupt Enable
flag
• Priority with in a level
 Stack OF 8051
• Stack operations are 8 bit wide
• PUSH and POP one byte of data pushed and
popped
• SP register is an 8 bit register
• Initialized to o7H after a reset
• SP is incremented first and the content of the
specified address is pushed
Stack OF 8051
Stack OF 8051
 Stack OF 8051
• Stack is Auto increment mode
• Always initialised in internal memory
• Stack memory size is limited
• In auto increment mode
• For implementing 16 bit two 8 bit operations
cascaded
 Module 6
• Addressing modes of 8051
Addressing modes of 8051
Addressing modes of 8051
• 1)Direct Addressing Mode
• In this mode the direct address of memory
location is provided in instruction to fetch the
operand.
• Only internal RAM and SFR's address can be used
in this type of instruction.
Ex: MOV A, 30H => Content of RAM address 30H
is copied into Accumulator.
•
• Direct Addressing Mode
• 2)Indirect Addressing mode
• The 8 bit address of an operand is stored in a
register and the register is specified in the
instruction
• The '@' sign indicates that the register holds the
address of memory location (registers R0,R1 and
SP can be used)
• fetch the content of memory location whose
address is provided in register.
Ex: MOV A,@R0 => Copy the content of memory
location whose address is given in R0 register.
• 3)Register Instructions

• Here the operand in contained in the specific

register of microcontroller.
• The user must provide the name of register from
where the operand/data need to be fetched.
• The permitted registers are A, R7-R0 of each
register bank.
• Ex: MOV A,R0-> content of R0 register is copied
into Accumulator.
• Register specific instructions
• Operend is implicitly specified using one of
the registers
• Some of the instructions always operate on a
specific register
• Immediate mode
• An immediate data ie a constant is specified in
the instruction