MICROCONTROLLER

Subject Code: 17MT43

Sem: Fourth MTR
TEXT BOOKS

 1. “The 8051 Microcontroller and Embedded Systems – using assembly and

C ”-, Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollin D. Mc
Kinlay; PHI, 2006 / Pearson, 2006
 2. “The 8051 Microcontroller”, Dr. K Uma Rao, Dr. Andhe Pallavi, Sanguine
Technical publishers, Bangalore-2009
Module 1: Microprocessors and microcontroller. Introduction, Microprocessors and
Microcontrollers, A Microprocessors survey. RISC & CISC CPU Architectures,
Harvard & Von-Neumann CPU architecture. The 8051 Architecture: Introduction,
8051 Microcontroller Hardware, Input / Output Pins, Ports and Circuits External
Memory, Counter and Timers, Serial Data Input / Output, Interrupts.
Module 2: Addressing Modes and Operations: Introduction, Addressing modes,
External data Moves, Code Memory, Read Only Data Moves / Indexed
Addressing mode, PUSH and POP Opcodes , Data exchanges, Byte level logical
Operations, Bit level Logical Operations, Rotate and Swap Operations,
Arithmetic Operations: Flags, Incrementing and Decrementing, Addition,
Subtraction, Multiplication and Division, Decimal Arithmetic.
Jump and Call Instructions: The JUMP and CALL Program range, Jumps, calls and
Subroutines, Interrupts and Returns.
Module 3: 8051 programming in C and Timers: Data types and time delays in
8051C, I/O programming, logic operations, data conversion programs, data
serialization.
Timer / Counter Programming in 8051: Programming 8051 Timers, Counter
Programming, programming timers 0 and 1 in 8051
Module 4: 8051 Serial Communication and Interrupts: Basics of Serial
Communication, 8051 connections to RS-232, 8051 Serial communication
Programming, Programming the second serial port, Serial port programming in
C. Interrupts Programming,8051 Interrupts, Programming Timer Interrupts,
Interrupt Priority in the 8051/52.
Module 5: 8051 Interfacing and Applications: Hardware & Software ( Assembly
code / C code) Interfacing of 8051 to simple switches and LEDs, LCD, ADC,
Stepper motor, DC motor, Temperature sensor, Wave form generation
Course outcomes

 CO1: have knowledge of Microcontrollers, Microprocessors, architecture ,

instruction set, memory concepts , delay generation ,interfacing of external
hardware peripherals.
 CO2: Describe the concepts of addressing modes , Assembly instruction
set.
 CO3: Analyze and design timer and counter code using assembly and c
code.
 CO4 : Apply the knowledge of serial communication to program 8051 as
serial port.
 CO5: Interface microcontroller with stepper, dc motor, ADC,DAC ,LED and
temperature sensor to realize real time application.
Microprocessors and
microcontroller
By: Ashwini T.P
Sr.Assistant Professor
Mechatronics Department
Syllabus Coverage for Module 1
 Introduction
 Microprocessors and Microcontrollers
 A Microprocessors survey.
 RISC & CISC CPU Architectures, Harvard & Von-Neumann CPU architecture.
 The 8051 Architecture:
 Introduction,
 8051 Microcontroller Hardware,
 Input / Output Pins,
 Ports and Circuits External Memory,
 Counter and Timers,
 Serial Data Input / Output, Interrupts.
 The prime use of microprocessor is to:
 Fetch the data
 Perform extensive calculations on that data
 Store the calculations on a mass storage device
 Display the results for the human use
 The primary use of the microcontroller is to control the operation of a
machine using a fixed program stored in a ROM.
 That does not change over the lifetime of the system.
 Harvard Architecture
 Code and data storage areas (address spaces) on separate buses
 Potentially more efficient
 Instructions execute in fewer cycles ,Since greater instruction parallelism
possible
 Instructions and data fetched simultaneously (new instruction fetches can
occur during prior instruction execution)
 8051 is a Harvard architecture as 8051 has seperate memories for data &
code
 Example: Microchip's PIC microcontroller
Princeton (Von Neumann) Architecture
 All memory space on same bus
 Every location has unique address
 So instructions and data treated the same way
 Possible bottleneck between instruction and data fetches
 Von neuman arhitecture advocates the use of same memory for code &
data ex.8085
8051 Block Diagram
Specific Features

 8 bit cpu with registers A and B

 16 bit PC and DPTR(data pointer).
 8 bit program status word(PSW)
 8 bit Stack Pointer
 4K Internal ROM
 128bytes Internal RAM
- 4 register banks each having 8 registers
16 bytes,which may be addressed at the bit level.
80 bytes of general purpose data memory

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Specific Features

 32 i/o pins arranged as 4 8 bit ports:P0 to P3

 Two 16 bit timer/counters:T0 and T1
 Full duplex serial data receiver/transmitter
 Control registers:TCON,TMOD,SCON,PCON,IP and IE
 Two external and Three internal interrupt sources.
 Oscillator and Clock Circuits.

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8051 Programming Model
 The programming model of the 8051 is a collection of
8- and 16-bit registers and 8-bit memory locations.
 Most of the registers have a specific function; those that do occupy an individual
block with a symbolic name, such as A or THO or PC.
 Others, which are generally indistinguishable from each other, are grouped in a larger
block, such as internal ROM or RAM memory.
 Each register, with the exception of the program counter, has an internal 1-byte ad-
dress assigned to it.
 Some registers (marked with an asterisk * in Figure 3) are both
byte and bit addressable.
 That is, the entire byte of data at such register addresses may be
read or altered, or individual bits may be read or altered.
 Software instructions are generally able to specify a register by its address, its symbolic
name, or both.
 P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)

8051
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)

PIN
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)

DESCRIPTION
P1.6 7 34 P0.5(AD5)
P1.7 8 8051 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
Pins of 8051

 Vcc（pin 40）：
 Vcc provides supply voltage to the chip.
 The voltage source is +5V.
 GND（pin 20）：ground
 XTAL1 and XTAL2（pins 19,18）：
 These 2 pins provide external clock.

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 Pins of 8051

 RST（pin 9）：reset
 It is an input pin and is active high（normally low）.
Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.

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Pins of 8051

 /EA（pin 31）：external access

 The /EA pin is connected to GND to indicate the code is stored
externally.
 For 8051, /EA pin is connected to Vcc.
 “/” means active low.
 /PSEN（pin 29）：program store enable
 This is an output pin and is connected to the OE pin of the ROM

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Pins of 8051

 ALE（pin 30）：address latch enable

 It is an output pin and is active high.
 8051 port 0 provides both address and data.
 The ALE pin is used for de-multiplexing the address and data by
connecting to the G pin of the 74LS373 latch.
 I/O port pins
 The four ports P0, P1, P2, and P3.
 Each port uses 8 pins.
 All I/O pins are bi-directional.

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8051 Oscillator and Clock
 The heart of the 8051
 Pins XTAL1 and XTAL2 are provided for connecting a resonant network to
form an oscillator.
 Typically a quartz crystal and capacitors are employed.
 The crystal frequency is the basic internal clock frequency of the
microcontroller.
 8051 designs can run at a specified min and max frequencies i.e, 1-16 MHz.
 The clock frequency “f” establishes the smallest intervals of time within the
microcontroller called pulse “P” time.
 Machine cycle is the smallest interval of time to accomplish any simple
instruction or part of a complex instruction.
 The machine cycle is itself made up of 6 states.
 A state is a basic time interval for discrete operations of the microcontroller
such as : fetching an opcode byte, decoding an opcode, executing an
opcode or writing a data byte.
 Two oscillator pulses define each state.
 To calculate the time any particular instruction will take to be executed,
find the number of cycles “C”. The time to execute that instruction is then
found by multiplying “C” by 12 and dividing the product by the crystal
frequency:
 Tinst= C*12d/crystal frequency
 Ex: if the crystal frequency is 16MHz, time to execute ADD A, R1 one cycle
instruction is 0.75 micro seconds.
Program Counter
 The 8051 contains two 16 bit registers: the program counter (PC) and the data
pointer (DPTR).
 Each is used to hold the address of a byte in the memory.
 Program instruction bytes are fetched from locations in memory that are
addressed by PC.
 The PC is automatically incremented after every instruction byte is fetched.
 Since PC is 16 bit wide, 8051 can access program from address 0000H to
FFFFH, a total of 64Kbytes of code.
 The content of PC may be altered by certain instructions like CALL, RET etc
 PC is the only register which does not have an internal address
 By default the PC is set to 0000H on reset of the computer.
DATA POINTER (DPTR)

 16 bit register made of two 8 bit register called DPH (High) and DPL (low).
 It is an index register that provide access to external memory.
 DPH and DPL hold the higher order byte and lower order byte of the
address.
 DPH and DPL are assigned internal address separately (DPH:83H and
DPL:82H)
A and B register
 These two registers hold the result of many arithmetic and logical operation
of the CPU.
 The Accumulator (A) is used in many operations including addition,
subtraction, integer multiplication and division.
 It is bit addressable register.
 It is also used for all data transfer between 8051 and external memory.
 Register B may be used as a location where data may be stored.
 It is also used with register A for multiplication and division operation and
has no other function.
 PROGRAM STATUS WORD(PSW)
 8 bit register
 Also referred to as flag register.
 It indicates certain condition like status of carry, parity sign etc after
execution of some instruction
Internal Memory
 8051 has internal ROM and RAM .
 Aditionary memory can be added externally using suitable circuits.
 8051 has a Hardvard architecture, which uses same address in different
memories for code and data.
Internal RAM
STACK AND STACK POINTER

 Stack refers to an area of internal RAM to store information temporarily.

 The information could be data or an address.
 The Stack Pointer (SP) is an 8 bit register used by 8051, to hold an internal
RAM address that is called the top of the stack.
 It is the address of the location in internal RAM where the last byte of data
was stored by the stack operation.
 There are two operations associated with stack:
 The PUSH operation places a data on stack.
 SP is incremented and then data is stored

 The POP operation gets the data from the stack.

 Data is retrieved from the location indicated by SP and then SP is decremented.
 The stack pointer is set to 07H by default on reset.

pop
push

stack pointer

stack
Special Function Registers

 The 8051 operations that do not use the internal 128 byte internal RAM
address from 00H to 7FH are done by a group of specific internal registers,
each called as Special Function Registers (SFR),
 Which may be addressed much like internal RAM, using addresses 80H to
FFH.
Internal ROM
 Data and program code memory can be in two entirely different physical
memory entities.
 Each has the same address range
 A block of internal program code contained in a internal ROM occupies
code address space 0000h to 0FFFh.
 PC is used to address from 0000h-FFFFh.
 Program address higher than 0FFFh – will cause 8051 to fetch code bytes
from external program memory.
 /EA to ground cause to fetch from external memory address 0000h-FFFFh.
Input/Output Pins, Ports and Circuits
 Each port has a D type output latch for each pin.
 The SFR for each port is made up of these eight latches.
 It can be addressed at the SFR address for that port.
 Eight latches for port 0 are addressed at location 80h.
 Port 0 pin 3 is bit 2 of the P0 SFR.
Port 0 Pin Configurations
Port 1Pin Configurations
Port 2 Pin Configurations
Port 3 Pin Configurations
External memory
TCON Register:

 TF1: Timer 1 overflow flag.

 TR1: Timer 1 run control bit.
 TF0: Timer 0 overflag.
 TR0: Timer 0 run control bit.
 IE1: External interrupt 1 edge flag.
 IT1: External interrupt 1 type flag.
 IE0: External interrupt 0 edge flag.
 IT0: External interrupt 0 type flag.
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 TMOD Register:

 Gate : When set, timer only runs while INT(0,1) is high.

 C/T : Counter/Timer select bit.
 M1 : Mode bit 1.
 M0 : Mode bit 0.

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Timers and Counters
Timer Modes of operation
 Timer 0 Mode 0
 Timer 0 Mode 1
 Timer 0 Mode 2
 Timer 0 Mode 3
Interrupts
 An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service.

Interrupts vs. Polling

 A single microcontroller can serve several devices.
 There are two ways to do that:
 interrupts
 polling.
 The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
 Time

72
Main program (base level, foreground)

Program execution without interrupts

Interrupt ISR
ISR ISR
level execution

Base-level Main Main Main Main

execution

Interrupt (occurs asynchronously)

Return from interrupt instruction
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 Steps in executing an interrupt
 Finish current instruction and saves the PC on stack.

 Jumps to a fixed location in memory depend on type of interrupt

 Starts to execute the interrupt service routine until RETI (return from
interrupt)

 Upon executing the RETI the microcontroller returns to the place where
it was interrupted. Get pop PC from stack
 Interrupt Priorities
 What if two interrupt sources interrupt at the same time?
 The interrupt with the highest PRIORITY gets serviced first.
 All interrupts have a power on default priority order.
1. External interrupt 0 (INT0)
2. Timer interrupt0 (TF0)
3. External interrupt 1 (INT1)
4. Timer interrupt1 (TF1)
5. Serial communication (RI+TI)
 Priority can also be set to “high” or “low” by IP reg.
Registers associated with interrupts

 Interrupt Enable (IE)

 Interrupt Priority (IP)
Reset
 This type of interrupt is called un maskable.
 Reset is an absolute command to jump to program address 0000H and
commence running from there.
Interrupt Control
 The IE register holds the programmable bits that can enable or disable all
the interrupts as a group, or if group is enabled.
 Each individual interrupt source can be enabled or disabled.
 Setting the priorities among the competing interrupts that may occur
simultaneously.

Interrupt Enable or Disable:

 Bits in the IE register are set to 1 if the corresponding interrupt source is
enabled.
 It is set to 0 to disable the interrupt source.
 Bit EA is a master or global bit that can enable or disable all of the
interrupts.
Interrupt Priority
 IP bits determine if any interrupt is to have high or low priority.
 Bit set to 1 give the accompanying interrupt a high priority.
 Bit 0 assigns a low priority
 Interrupt with high priority can interrupt the process with low priority.
 Lower priority interrupt continues after the higher is finished.
 Following ranking is used:
1. IE0
2. TF0
3. IE1
4. TF1
5. Serial= RI or TI
For example: the serial interrupt could be given the highest priority by setting
PS bit in IP to 1 and all others to 0.
Interrupt Destination
 Each interrupt source causes the program to do a hardware call to one of
the dedicated address in the program memory.
 It is the responsibility of the programmer to place a routine at the address
that will service to the interrupt.
Software Generated Interrupts
 Program itself can cause the interrupts of any kind to be generated unless
blocked.
 Setting the Interrupt flag to 1 using programming instruction.
Interrupt Enable Register :

 EA : Global enable/disable.
 --- : Undefined.
 ET2 :Enable Timer 2 interrupt. (in 8052)
 ES :Enable Serial port interrupt.
 ET1 :Enable Timer 1 interrupt.
 EX1 :Enable External 1 interrupt.
 ET0 : Enable Timer 0 interrupt.
 EX0 : Enable External 0 interrupt.
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Interrupt Priority Register :

-- -- PT2 PS PT1 PX1 PT0 PX0

 PT2 :Prioritize Timer 2 interrupt (8052 only )

 PS :Prioritize Serial port interrupt. Default Priorities
 PT1 :Prioritize Timer 1 interrupt. Highest: IE0
 PX1 :Prioritize External 1 interrupt. TF0
 PT0 :Prioritize Timer 0 interrupt. IE1
TF1
 PX0 : Prioritize External 0 interrupt. Lowest: Serial

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 Basics of serial communication
Parallel: expensive - short distance – fast
Serial :cheaper– long (two different cities by modem)-slow
Basics of serial communication
 Start and stop bits
When there is no transfer the signal is high
Transmission begins with a start (low) bit
LSB first
Finally 1 stop bit (high)
Data transfer rate (baud rate) is stated in bps
bps: bit per second
Registers associated with serial
communication
 Serial Port Control (SCON)
 Power Mode Control (PCON)
 SBUF
Serial Communication & SFR

SM0 & SM1 : Mode bits : Mode 0: Shift Register; baud =f/12

Mode 1: 8 bit UART; baud = variable

SM0 Mode
SM12: 9 SM2
bit UART;REN
baud =f/32
TB8 or RB8
f/64 TI RI
Mode 3: 9 bit UART; baud=variable
SM2: Multiprocessor communication bit, set/cleared by program
REN: Receive enable bit
TB8: Transmitted bit in mode 2 and 3
RB8: Received bit in mode 2 and 3, stop bit in mode 1,
TI: Transmit interrupt flag, set by hardware. To be cleared by program
RI: Receive interrupt flag

Baud Rate= (2 smod X oscillator frequency) / (32 X12X(256-TH1))

(timer 1 is run in mode 2)

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Power Control SFR
PCON SFR:
SMOD -- -- -- GF1 GF0 PD IDL

SMOD : Serial Baud Rate Modify bit

GF1 & GF0 : General purpose user flag bits
PD: Power Down bit ; Set to 1 by program to enter power down configuration
IDL: Idle mode bit: Set to 1 by program to enter idle mode configuration

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