Ethernet 2 Chapter

ETHERNET
CHAPTER 1
Presented By
CHANDAN G M
©2017 Graphene Semiconductor Confidential

CONTENTS
 Introduction
 Evolution of Ethernet
 Ethernet frame format
 Ethernet in physical and datalink layer
 Ethernet in MAC layer
 CSMA/CD
 Ethernet vs wi-fi
 NIC and role of Network interface controller in Ethernet
 Ethernet Initialization

INTRODUCTION
Ethernet:
 Ethernet is one of the most popular physical layer

LAN technology.
 Ethernet is used for connecting wired local area
networks (LANs), enabling devices to communicate
with each other via a protocol.
 Ethernet operates in the data link layer and the
physical layer.
 It is a family of networking technologies that are OSI layer TCP/IP
defined in the IEEE 802.2 and 802.3 standards.
Ethernet supports data bandwidths of:
• 10 Mb/s
• 100 Mb/s
• 1000 Mb/s (1 Gb/s)
• 10,000 Mb/s (10 Gb/s)

ETHERNET STANDARDS
Supplement Year Description
802.3a 1985 10Base-2 (thin Ethernet)

802.3c 1986 10 Mb/s repeater specifications (clause 9)
802.3d 1987 Fiber Optic Inter Repeater Link (FOIRL).Use of two
fibre optic cables
802.3i 1990 10Base-T (twisted pair)
802.3j 1993 10Base-F (fiber optic)
802.3u 1995 100Base-T (Fast Ethernet and autonegotiation)
802.3x 1997 Full duplex
802.3z 1998 1000Base-X (Gigabit Ethernet)
802.3ab 1999 1000Base-T (Gigabit Ethernet over twisted pair)
802.3ac 1998 VLAN tag (frame size extension to 1522 bytes)
802.3ad 2000 Parallel links (link aggregation)
802.3ae 2002 10-Gigabit Ethernet
802.3ah 2004 Ethernet in the first mile
802.3as 2005 Frame expansion
802.3at 2005 Power over Ethernet Plus
802.3an 2006 10GBase-T
802.3aq 2006 10GBase-LRM, Ethernet over multimode fiber

EVOLUTION OF ETHERNET
 Ethernet, a physical layer local area

network (LAN) technology, is nearly
30 years old. In the last three decades,
it has become the most widely used
LAN technology because of its speed,
low cost, and relative ease of
installation.
 In 1973, Robert Metcalfe and David Boggs at Xerox Corporation in

Palo Alto, they added ALHOA network principles and created the world’s
first Local Area Network (LAN) called Ethernet.
 Initially named ALTO ALOHA, the name was later changed to Ethernet.
This first version of Ethernet ran at speeds up to 2.94 Mbps. later this
version is not successfully commercialized.
 The first commercial Ethernet was by DEC, Intel, and Xerox (DIX) in
1980 as Ethernet,Version 1 called as a Ethernet DIX80.

 Version 2, was released in 1982, Ethernet DIX82. Ethernet, Version 2 is
the standard of Ethernet technology that is in use today.
 In 1983 IEEE launches first IEEE standard Ethernet Technology. Which is

developed by 802.3 group of IEEE 802 commitee, named as IEEE 802.3
(CSMA/CD).

ETHERNET FRAME FORMAT
DIX Frame:
Destination
Preamble Source address Type Data CRC
address
8 bytes 6 bytes 2 bytes 46 to 1500 bytes 4 bytes
6 bytes
IEEE 802.3 Ethernet frame:
SFD Destination Source LLC | Data | Pad

Preamble Length FCS
1 address address 46 to 1500 bytes
7 bytes 2 bytes 4 bytes
byte 6 bytes 6 bytes
HEADER PAYLOAD TRAILER
 It is also called as packet delivery system.

 Mainly it consist of 3 parts:
1. Header (Preamble to Length)

2. Payload (LLC to Pad)
3. Trailer (FCS)

HEADER:
Preamble : (7 bytes)
 Sets bit timing and signals that a frame is being sent (Ex:10Mb/s).
 It is a series of 56 bits alternating with 1's and 0's, these bits are used for
synchronization and give each participant the time to observe the activity on the
bus before the actual data arrives.
 It is the starting field that provides alert and timing pulse for transmission.
SFD (start frame delimiter) : ( 1 bytes)

 It is a 8 bit sequence (10101011).
 The last byte of the preamble, indicates to the receiver that the actual data is on its
way.
 Normally when we are using 100Mb/s or 1000Mb/s Ethernet, preamble and sfd not
used.
Destination Address : (6 bytes)

 It is 48 bit Receiving hardware MAC address.
 This field identifies the station or stations that have to receive the message.
 The DA can be an individual, multicast or broadcast.

Source Address : (6 bytes)
 Its a 48 bit transmitting hardware MAC address.
 This field identifies the station from where the message originates.
Type : (2 bytes)
 This field drawn a difference between Ethernet 2 (DIX standard) and the IEEE
802.3.
 In Ethernet 2, the higher level protocols (Ex: IP-0x800h, ARP-0x806h, RARP-
0x835h) are present which uses an Ethernet frame to send data.
Length : (2 bytes)
 This field is used only by IEEE 802.3.
 which indicates length of data field (number of LLC data bytes)
 or which defines how many actual data in bytes able to send.

PAYLOAD:
LLC:
Governs the assembly of data at the data link (layer 2) level.
It also specifies actual length of the data to be sent.
Data: (46 To 1500bytes)

The data field contains the data to be sent only the length has to be a
minimum of 46 bytes and not more than 1500 bytes.
PAD:
When data is less than 46 bytes then this field pads 0’s in order to reach
the minimum data field of 46 bytes.
TRAILER:
CRC/FCS:
Detects transmission errors and provides quality of service at receiving
end.

ETHERNET IN PHYSICAL AND DATALINK LAYER
 Ethernet works in lower two layers in OSI model

they are:
 Physical layer
 Data link layer
ETHERNET IN PHYSICAL LAYER
1. Physical layer:
 sending and receiving the serial bit streams over the physical medium (ex: cables,
repeaters (hub,switch, gate...etc))
 Helps in Detecting collisions.

NETWORK DEVICES
These are the devices mainly used in building networks like Hubs, Bridges, Switches and
Routers.
1. Hubs:
 A hub is a very simple (or dumb) device.
 A hub is basically a multiport repeater. A hub connects multiple wires coming from
different branches,
There are mainly two types of hubs:
Passive: The signal is forwarded as it is (so it doesn’t need power supply).

Active: The signal is amplified, so they work as repeaters. In fact they have been
called multiport repeaters. (use power supply)
2. Switch:
 Switches on the other hand are more advanced and it is a data link layer device, It is
design that can boost its efficiency(large number of ports imply less traffic) and
performance.
 Switch can perform error checking before forwarding data, that makes it very efficient as
it does not forward packets.
 Based on the MAC address of destination operation take place, hence it reduces traffic
and collision.
3. Bridge:
A bridge operates at data link layer. A bridge is a repeater, It is also used for
interconnecting two LANs working on the same protocol.
4. Routers:
Routers are used to connect different LANs or a LAN with a WAN (e.g. the internet).
Routers come with hub or switch technology to connect computers directly, Now a
days.
5. Repeaters:
Repeaters are simple devices that work at the physical layer of the OSI. They regenerate
signals (active hubs does that too).

6. Brouter: Advanced Technology
 It is also known as bridging router is a device which combines features of
both bridge and router.
 It can work either at data link layer or at network layer. Working as router,
it is capable of routing packets across networks and working as bridge, it is
capable of filtering local area network traffic.

NETWORK TOPOLOGIES
1. Point to point Topology
2. Bus Topology 3. Star Topology

4. Ring Topology 5. Mesh Topology
6. Hybrid Topology

ETHERNET IN DATALINK LAYER
It consist of two parts:

1. LLC sublayer
2. MAC sublayer
LLC:
 The Ethernet LLC sublayer handles the communication between the upper layers and
the lower layers. The LLC sublayer takes the network protocol data, which is typically
an IPv4 packet,and adds control information to help deliver the packet to the
destination node.
MAC:
 MAC constitutes the lower sublayer of the data link layer. MAC is implemented by
hardware, typically in the computer NIC. The specifics are specified in the IEEE 802.3
standards.
 Ex: when you are using bus topology (if collision occurs) that time Channel access
control Mechanisms applied by MAC layer.
 Different kind of channel access control mechanisms are applied by the MAC layer
for media access are CSMA/ CD, CSMA/ CA.

ETHERNET IN MAC LAYER
 MAC sublayer provides addressing and channel access

control mechanism, which makes it possible to
communicate with in a multiple network.
 Ethernet modules use the Address Resolution Protocol

(ARP) to obtain MAC addresses for outgoing Ethernet
frames.
 Ethernet uses a type field to tell the receiver what to do

with the frame.

ARP (Address resolution protocol):

Functions of MAC Layer
 It is responsible for encapsulating frames so that they are suitable for transmission
via the physical medium.
 It also performs collision resolution and initiating retransmission in case of

collisions.
 It generates the frame check sequences and thus contributes to protection against
transmission errors.

MAC (MEDIA ACCESS CONTROL) ADDRESS
 Each Ethernet network has network interface card (NIC) has a unique identifier called
MAC address assigned by card manufacturer (physical address).
 Here each MAC address is a 48 bit number
 First 24 bits identify the manufacturer this part called manufacturer ID or organized
unique identifier (OUI) [IEEE registration authority].
 Second part is assigned by manufacturers, this number is usually programmed into the
hardware so that it cannot be changed.
 EX: OUI
CC:46:D6 (cisco)
3C:D9:2B (Hewlett packard)
 EX: NIC (may be hypen-hex,colen-hex,period separated-hexdecimal notation)

00-0a-83-b1-c0-8e
00:0a:83:b1:c0:8e (Linux os)
000.a83.b1c.08e (cisco system)

TYPES OF MAC ADDRESS
They are:
1. Unicast
2. Multicast
3. Broad cast
1. Unicast:
 A Unicast addressed frame is only sent out to the interface leading to specific NIC. If
the LSB (least significant bit) of first octet of an address is set to zero, the frame is
meant to reach only one receiving NIC.
 MAC Address of source machine is always Unicast.

2. Multicast:
 Multicast address allow the source to send a frame to group of devices.
 In Layer-2 (Ethernet) Multicast address, LSB (least significant bit) of first octet of an
address is set to one. IEEE has allocated the address block 01-80-C2-xx-xx-xx.

3. Broadcast:
 It is Similar to Network Layer, Broadcast is also possible in data link layer.
 Ethernet frames with address of FF-FF-FF-FF-FF-FF called broadcast address.
Frames which are destined with MAC address FF-FF-FF-FF-FF-FF will reach to
every computer belong to that LAN segment.

In case if Data Lost during data
transmission because of some
Collision what next.......?

CSMA/CD
CSMA (carrier sense multiple access/collision detection)
 It is a media-access control method widely used in

Ethernet LAN technology.
 CSMA/CD standard defines how Ethernet frames get on
to an Ethernet network.
 Minimum time gap required for frame transmission is 9.6
micro seconds. Fig 1 CSMA/CD
 Problem: when more than one station transmits the data

at the moment. There will be collisions in the data from
different stations.
 Solution: CSMA/CD which helps us to detect collision

and gives effect way of communication.

Working of CSMA/CD:
Ready to Transmit
Listen to medium
No
Carrier Detect?
Yes
Transmit Data Wait Back off - Protocol
No Collission Detect? Yes Transmit JAM sequence
Transmission
Complete
Step 1: Check if the sender is ready for transmitting data packets.
Step 2: Check if the transmission link is idle or not?
 Sender has to keep on checking if the transmission medium is idle.

 Sender sends dummy data on the link.
 If it does not receive any collision signal, then link is idle state.
 If it senses that the carrier is free and there are no collisions, then it sends the data.
Step 3: Transmit the data & check for collisions.
Sender transmits its data on the link. CSMA/CD does not use ‘Acknowledgement’
system. It checks for the successful and unsuccessful transmissions through collision
signals. During transmission, if collision occurs then transmission is stopped. The station
then transmits a Jam signal onto the link and waits for random time interval (backoff-
wait) before it resends the frame.
Step 4: If no collision was detected , then sender completes its frame or data transmission
and resets the counters.

Backoff - Process (waiting Time)
Working of Backoff Algorithm in CSMA/CD:
 It is one of the algorithm generally used in Ethernet to
schedule re-transmissions of data after collisions. or It
is mainly used for to Generate a Random interval of
Time.
or
 Backoff algorithem is used to avoid infinite loop of
collisions which leads to deadlock situations.
 Backoff algorithrm tells how much time the station

should wait to re-transmit in order to avoid collisions.
 Backoff time is Given by:

Waiting time = K * Tslot
where:
n = collision number or re-transmission
number. K = [0, 2n – 1 ]
After a collision, time is divided into discrete slots
(Tslot) equal to 2t. t is the maximum propagation delay
in the network.

Case 1: when n =1 both packets are same
when A=0, B=0
W.T for A = 0 * Tslot = 0
W.T for B = 0 * Tslot = 0
So both stations will transmit at the same time and hence collision occurs.
when A=0, B=1
W.T for A = 0 * Tslot = 0
W.T for B = 1 * Tslot = Tslot
so A transmits the packet and B waits for time Tslot for transmitting and hence A wins.
when A=1, B=0
W.T for A = 1 * Tslot = Tslot
W.T for B = 0 * Tslot = 0
so B transmits the packet and A waits for time Tslot for transmitting and hence B wins.
when A=1, B=1
W.T for A = 1 * Tslot = Tslot
W.T for B = 1 * Tslot = Tslot
So both will wait for the same time Tslot and then transmit. Hence, collision occurs.
Conclusion:
Probability that A wins = 1/4
Probability that B wins = 1/4
Probability of collision = 2/4 ....so probality of collision is more, hence go for case 2.

Case 2: when n=1 for A and n=2 for B
Assume n becomes 1 for packet 2 of A and becomes 2 for packet 1 of B.
For packet 2 of A, K = {0, 1}
For packet 1 of B, K = {0, 1, 2, 3}
Conclusion:
Probability that A wins = 5/8

Probability that B wins = 1/8
Probability of collision = 2/8
Note:
so compared to previous case probability of collision is very less.

COLLISION OF THE FIRST BIT CSMA/CD
 A starts send the first bit of its frame at t1, C sees the channel idle at t2, and
starts sending its frame at t2. C detects A’s frame at t3 and aborts
transmission. A detects C’s frame at t4 and aborts its transmission.
Transmission time for C’s frame is therefore t3-t2 and for A’s frame is t4-t1.
 The frame transmission time (Tfr) should be at least twice the maximum
propagation time (Tp) .....[Tfr>=2Tp]

Collision and abortion in CSMA/CD

HALF DUPLEX AND FULL DUPLEX ETHERNET
Half Duplex Full Duplex
Only one wire is used to connected the 2 wires are used to connected the
networks and transmit data networks and transmit data
The chances of collison if client and There is no chance of collision
server transmit a data simultaneously
It uses CSMA/CD protocol CSMA/CD is not required hence data
transmission rate is 100 percent

ETHERNET VS WIFI
Wifi (wireless) is more convenient than Ethernet Technology (wired), but still Ethernet has
more advantages compared to wifi based on the following factors:
• Speed
• Latency
• Reliable
• Security
 Speed:
According to the IEEE standards like 802.11ac and 802.11n, wifi offer
maximum speed of 866.7 Mb/s and 150 Mb/s, respectively. In order to handle
our daily tasks Wifi good.
But Ethernet can theoretically offer up to 10 Gb/s, if you used Cat6 cable. The
speed Ethernet depends on the type of Ethernet cables using. The Cat5e cable in
common use supports up to 1 Gb/s.
 Latency:
The time taken for a packet to be transferred across a network.
Wi-Fi has more latency compared Ethernet connection.(Ex: online games).

ETHERNET
 Reliable: VS WIFI
Ethernet is more reliable connection compared to WI-FI.
 Security:
Ethernet is good compared to wifi
When to use Ethernet and wi-fi:
Ethernet:
when desktop PC or server sits in a single place, Ethernet may be a good

option. If you want better quality streaming Assuming it’s easy enough to plug
the devices in with an Ethernet cable, you’ll get a more consistently solid
connection.
wi-fi:
Wi-Fi convenience, If a device needs to move around or you just don’t want to
run a cable to it, Wi-Fi is the right choice.

ETHERNET
CONTROLLER
CHAPTER 2

NIC (NETWORK INTERFACE CONTROLLER)
 NIC establishes a link between a computer and a network, and then manages that link it
is also called as ethernet card or network adapter.
 The primary task of a network interface card is to enable the host system to transfer
data between main memory and the network.
 NICs connect to the host system via a local interconnect such as the Peripheral
Component Interconnect (PCI) bus. A device driver running on the host system is
responsible for communicating with the NIC over this interconnect.

Types of NIC
1. Ethernet NIC:
 Provides interface between computer and the local network or the other
networks on internet.
2. Wireless network NIC:
 Wireles network adapters enables devices to communicate with each other
over wifi or other wireless networking protocols.
Note: Each NIC has a unique hardware network address called MAC.

NETWORK INTERFACE CONTROLLER
Architecture:
Host- processor
DMA Controller MAC
Full duplex
Link
Local memory
Main memory Buffer - rx
Buffer - tx
PCI interface

PCI FEATURES
It is a local computer bus for attaching hardware devices in a computer.
 Signaling Environment : Supports both 3.3 and 5 volt signaling environments.

 Speed: It can transfer up to 132 MB per second.
 Synchronous bus architecture : PCI is a synchronous bus where data transfer
takes place according to a system clock.
 32 and 64 bit addressing : The PCI bus also supports 64 bit addressing with the
same 32 bit connector.
 Large bandwidth : It can handle both 32 bit as well as 64 bit data hence the
maximum bandwidth will be 132 MB per second.

Functions of NIC
1. Data traversing parallel to serial and vice versa
2. Acts as a gatekeeper: Data pass through NIC and on to CPU (may be

unicast or broad cast based on MAC address)

ROLE
Data Receiving
OF NIC IN ETHERNET
4
Host- processor 1
DMA Controller MAC
Network
3 2
Main memory Local memory
Packet Buffer - rx
Packet
Buffer - tx
PCI interface

DATA RECEPTION
Data received from network
Packet stored in received buffer
NIC transfer received packets via DMA

from buffer to main memory
NIC notifies host system via an interrupt

once the data transfer completed

Data Transmission
1
Host- processor 4
DMA Controller MAC
Network
Main memory Local memory

2
Buffer - rx
Packet
Buffer - tx
Packet
PCI interface

DATA TRANSMISSION
Creation of Transmission Buffer
Transmission of control buffer to NIC
NIC checks descriptor and initiates DMA

to transfer data from main memory to tx
buffer
Data reading done by MAC and transfer

data over a network
NIC notifies the system regarding data

transferred

ENC28J60

Description about ENC28J60
1. Control Registers which are used to control and monitor the ENC28J60.
2. RAM buffer for received and transmitted data packets.
3. Arbiter to control the access to the RAM buffer when requests are made from DMA,
transmit and receive blocks.
4. Bus interface that interprets data and commands received via the SPI interface.
5. MAC (Medium Access Control) implements IEEE 802.3 compliant MAC logic.
6. PHY (Physical Layer) module that encodes and decodes the analog data that is
present on the twisted pair interface.
The device also contains other support blocks, such as the oscillator, on-chip voltage
regulator, level translators to provide 5V tolerant I/Os and system control logic.

PIN DESCRIPTION Pin Description
CS Chip select
INT INT interrupt output pin.
VSSRX Ground reference for PHY

RX
VDDOSC positive 3.3V supply for
oscillator.
VSSOSC Ground reference for
oscillator.
VSSPL Ground reference for PHY
PLL.
VDDPLL Positive 3.3V supply for PHY
PLL
RBIAS Current bias for PHY

MEMORY LAYOUT
All memory in the ENC28J60 is implemented as static RAM. There are three types of
memory in the ENC28J60.
 Control Registers
 Ethernet Buffer
 PHY Registers

CONTROL REGISTERS
 The Control Registers provide the main interface between the host controller and
the on-chip Ethernet controller logic.
 The Control Register memory is partitioned into four banks, selectable by the bank
select bits BSEL1:BSEL0 in the ECON1 register. Each bank is 32 bytes long and
addressed by a 5-bit address value.
 Control registers for the ENC28J60 are generically grouped as ETH, MAC and
MII registers.
 The last five locations (1Bh to 1Fh) of all banks point to a common set of registers:
EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers used in
controlling and monitoring the operation of the device.

ETHERNET BUFFER ORGANIZATION
Transmit Buffer Start
(ETXSTH:ETXSTL) 0000h
Buffer Write Pointer

(EWRPTH:EWRPTL) AAh Transmitt buffer data (WBM AAh)
Transmit Buffer End
(ETXNDH:ETXNDL)
Transmitt
Receive Buffer Start
(ERXSTH:ERXSTL) Buffer
Note: The Ethernet buffer contains transmit and
receive memory used by the Ethernet controller.
Receive Buffer
(Circular FIFO)
Buffer Read Pointer

(ERDPTH:ERDPTL) 55h Receive buffer data (RBM 55h)
Receive Buffer end 1FFFh

(ERXNDH:ERXNDL)

PHY REGISTERS
 The PHY registers provide configuration and control of the PHY module, as well as
status information about its operation. All PHY registers are 16 bits in width. There are
a total of 32 PHY addresses.
MDIO: (Managemenet data input/output)
 The PHY registers are not directly accessible. Instead, access is accomplished through a
special set of MAC control registers that implement Media Independent Interface
Management (MIIM).
 The MII connects Media Access Control (MAC) devices with Ethernet physical
layer (PHY) circuits.
 The MAC device controlling the MDIO is called the Station Management Entity
(SME).

MDIO
WRITE
MDIO
READ

ETHERNET INITIALIZATION
Reset
Enable TX/RX FIFO
Set Filter Mode and CRC
MAC Initialization
PHY Initialization

PROGRAMMING INITIALIZATION (FIFO, FILTER, CRC)
Soft Reset
Clear ECON 1
Enable RX FIFO
Enable TX FIFO
Start: ERXSTL=1
Start: ETXSTL=1
End: ERXNDL=1
End: ETXNDL=1
ERXRDPTL=1
Filter mode and set CRC
ERXFCON_UCEN=1
ERXFCON_BCEN=1
ERXFCON_CRCEN=1

PROGRAMMING MAC INITIALIZATION
Enable MAC Receive
MACON1_MARXEN=1
MACON1_TXPAUS=1
MACON1_RXPAUS=1
Enable Automatic padding and CRC Operation
Full duplex mode Half duplex mode
MACON3_PADCFG0=1 MACON3_PADCFG0=1
MACON3_TXCRCEN=1 MACON3_TXCRCEN=1
MACON3_FRMLNEN=1 MACON3_FRMLNEN=1
MACON3_FULDPX=1 Set IFG MAIPGL=1
Set IFG MAIPGL=1
Set maximum packet size
MAX_FRAMELEN=1
(1518 bytes)

PROGRAMMING PHY INITIALIZATION
Full duplex
IF PHCON1_PDPXMD=1
PHCON2=0x00
Half duplex
ELSE PHCON1=0x00
PHCON2_HDLDIS=1

CONTROL REGISTERS
ECON 1 (Ethernet control register 1)
Function:The ECON1 register is used to control the main functions of the ENC28J60.
Receive enable, transmit request, DMA control and bank select bits can all be found in
ECON1.
Bit no Flag Description
0 BSEL 0 Bank select bits
1 BSEL 1 Bank elect bits
2 RXEN Receive enable bit
3 TXRTS Transmitt request to send bit
4 CSUMEN DMA checksum enable bit
5 DMAST DMA start and busy status bit
6 RXRST Receive logic reset bit

7 TXRST Transmitt logic reset bit

ECON 2 (Ethernet control register 2)
0 Unimplemented Read as 0
3 VRPS Transmitt request to send bit
4 RESERVED Maintained as 0
5 PWRSV Power save enable bit
6 PKTDEC Packet decrement bit
7 AUTOINC Automatic Buffer Pointer Increment Enable

bit

PHYSTAT REGISTER
PHSTAT 2 :physical layer status register.
0-4 Unimplemented Read as 0
5 PLRITY polarity status bits
9 DPXSTAT Phy duplex status bit
10 LSTAT Phy link status bit (up or down)
11 COLSTAT Phy collision status bit
12 RXSTAT Phy receive status bit
13 TXSTAT Phy transmitt status bit
14-15 unimplemented Read as 0

PHSTAT 1 :physical layer status register.
1 JBSTAT PHY Latching Jabber Status bit
2 LLSTAT PHY Latching Link Status bit
11 PHDPX Phy half duplex capable bit
12 PFDPX Phy full duplex capable bit
13-15 Unimplemented Phy receive status bit

MACON 1: MAC CONTROL REGISTER 1
0 MARXEN Mac receive enable bit
1 PASSALL Pass all received frames enable bit
2 RXPAUS Pause control frame reception enable bit
3 TXPAUS Pause control frame transmission enable bit
4 RESERVED Maintain as 0

MACON 3: MAC CONTROL REGISTER 3
0 FULDPX Mac full duplex enable bit
1 FRMLNEN Frame length checking enable bit
2 HFRMEN Huge frame enable bit
3 PHDREN Proprietary header enable bit
4 TXCRCEN Transmit crc enable bit
5-7 PADCFG2:PADC Automatic pad crc configuration bits

FGG0

PHCON 2: phy control register 2
0-7 Reserved Write as 0
8 HDLDIS Phy half duplex loopback disable bit
9 Reserved Write as 0
10 JABBER Jabber correction disable bit
11-12 Reserved Write as 0
13 TXDIS Twisted pair transmitter disable bit
14 FRCLNK PHY force linkup bit

PHCON 1: phy control register 1
7 Reserved Maintain as 0
8 PDPXMD Phy duplex mode bit
10 Reserved Maintain as 0
11 PPWRSV Phy power down bit
14 PLOOPBK Phy loo back bit
15 PRST Phy software reset bit

APPENDIX
SOFT RESET
static void enc28j60_soft_reset(struct enc28j60_net *priv)

{
spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);//0xff
* delay at least 1 ms instead */
udelay(2000);
}
FILTER MODE
/* default filter mode: (unicast OR broadcast) AND crc valid */
locked_regb_write(priv, ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN |

ERXFCON_BCEN);

TX FIFO
static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
{
struct device *dev = &priv->spi->dev;
if (start > 0x1FFF || end > 0x1FFF || start > end) {

if (netif_msg_drv(priv))
dev_err(dev, "%s(%d, %d) TXFIFO bad
parameters!\n", __func__, start, end);
return;
}
/* set transmit buffer start + end */
nolock_regw_write(priv, ETXSTL, start);

nolock_regw_write(priv, ETXNDL, end);
}

RX FIFO
static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
{
struct device *dev = &priv->spi->dev;
u16 erxrdpt;
if (start > 0x1FFF || end > 0x1FFF || start > end) {

if (netif_msg_drv(priv))
dev_err(dev, "%s(%d, %d) RXFIFO bad
parameters!\n", __func__, start, end);
return;
}
/* set receive buffer start + end */
priv->next_pk_ptr = start;
nolock_regw_write(priv, ERXSTL, start);
erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
nolock_regw_write(priv, ERXRDPTL, erxrdpt);
nolock_regw_write(priv, ERXNDL, end);
}

MAC INITIALIZATION
/* Enable MAC receive */
locked_regb_write(priv, MACON1,MACON1_MARXEN | MACON1_TXPAUS |

MACON1_RXPAUS);
/* enable automatic padding and CRC operations */
if (priv->full_duplex) {
locked_regb_write(priv, MACON3,
MACON3_PADCFG0 | MACON3_TXCRCEN |
MACON3_FRMLNEN | MACON3_FULDPX);

PHY INITIALIZATION
* Set the maximum packet size which the controller will accept*/
locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
/* Configure LEDs */
if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
return 0;
if (priv->full_duplex) {
if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
return 0;
if (!enc28j60_phy_write(priv, PHCON2, 0x00))
return 0;
} else {
if (!enc28j60_phy_write(priv, PHCON1, 0x00))
return 0;
if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
return 0;
}
if (netif_msg_hw(priv))
enc28j60_dump_regs(priv, "Hw initialized.");
return 1;
}

/* set inter-frame gap (non-back-to-back) */
locked_regb_write(priv, MAIPGL, 0x12);
/* set inter-frame gap (back-to-back) */
locked_regb_write(priv, MABBIPG, 0x15);
} else {
locked_regb_write(priv, MACON3,
MACON3_PADCFG0 |
MACON3_TXCRCEN |
MACON3_FRMLNEN);
locked_regb_write(priv, MACON4, 1 << 6); /*
DEFER bit */
/* set inter-frame gap (non-back-to-back) */
locked_regw_write(priv, MAIPGL, 0x0C12);
/* set inter-frame gap (back-to-back) */
locked_regb_write(priv, MABBIPG, 0x12);
}

Thank You

Ethernet 2 Chapter

Încărcat de

Informații document

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Ethernet 2 Chapter

Încărcat de

Drepturi de autor:

Formate disponibile

ETHERNET

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

 Ethernet is one of the most popular physical layer

©2017 Graphene Semiconductor Confidential

802.3a 1985 10Base-2 (thin Ethernet)

©2017 Graphene Semiconductor Confidential

 Ethernet, a physical layer local area

 In 1973, Robert Metcalfe and David Boggs at Xerox Corporation in

©2017 Graphene Semiconductor Confidential

 In 1983 IEEE launches first IEEE standard Ethernet Technology. Which is

©2017 Graphene Semiconductor Confidential

IEEE 802.3 Ethernet frame:

SFD Destination Source LLC | Data | Pad

HEADER PAYLOAD TRAILER

 It is also called as packet delivery system.

1. Header (Preamble to Length)

©2017 Graphene Semiconductor Confidential

SFD (start frame delimiter) : ( 1 bytes)

Destination Address : (6 bytes)

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

Data: (46 To 1500bytes)

©2017 Graphene Semiconductor Confidential

 Ethernet works in lower two layers in OSI model

ETHERNET IN PHYSICAL LAYER

©2017 Graphene Semiconductor Confidential

There are mainly two types of hubs:

Passive: The signal is forwarded as it is (so it doesn’t need power supply).

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

1. Point to point Topology

2. Bus Topology 3. Star Topology

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

It consist of two parts:

©2017 Graphene Semiconductor Confidential

 MAC sublayer provides addressing and channel access

 Ethernet modules use the Address Resolution Protocol

 Ethernet uses a type field to tell the receiver what to do

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

 It also performs collision resolution and initiating retransmission in case of

©2017 Graphene Semiconductor Confidential

 EX: NIC (may be hypen-hex,colen-hex,period separated-hexdecimal notation)

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential

 It is a media-access control method widely used in

 Problem: when more than one station transmits the data

 Solution: CSMA/CD which helps us to detect collision

©2017 Graphene Semiconductor Confidential

Transmit Data Wait Back off - Protocol

No Collission Detect? Yes Transmit JAM sequence

Step 2: Check if the transmission link is idle or not?

 Sender has to keep on checking if the transmission medium is idle.

Step 3: Transmit the data & check for collisions.

©2017 Graphene Semiconductor Confidential

 Backoff algorithrm tells how much time the station

 Backoff time is Given by:

©2017 Graphene Semiconductor Confidential

©2017 Graphene Semiconductor Confidential