Linear and Digital Integrated Circuits: Uni T - 1 Operati Onal Ampli Fier

LINEAR AND DIGITAL
INTEGRATED CIRCUITS
UNIT - 1
OPERATIONAL AMPLIFIER
CONTENTS
 Op Amp Applications.
 AC Characteristics.
 DC Characteristics.
 Comparators.
 Multivibrators.
Op-Amp Applications
With Negative feedback:
Linear applications Non linear applications
• Adders • Clippers
• Subtractors • Clampers
• Adder-Subtractor • Rectifiers
• Voltage to current converter • Peak detector
• Current to voltage converter • Sample and hold circuit
• Instrumentation amplifier • Log and antilog amplifier
• Analog computation, • Multipliers, etc.
Power amplifiers, etc
With Positive feedback:
• Multivibrators, Oscillators, Schmitt trigger etc.
Without feedback:
• Comparators
Scale Changer/Inverter
 If the ratio Rf/R1 = K, where K is a real constant, then the closed loop gain
ACL = -K i.e. the circuit can be used to multiply by a constant factor K.
 If Rf = R1, then ACL = -1 and the circuit is called an inverter i.e. the output is
180◦ out of phase with respect to input though the magnitudes are same.
Inverting Summing Amplifier
 Assume that op-amp is an ideal one, i.e. AOL = ∞ and Ri = ∞, and also
assume that the input bias current is zero, then there is no voltage drop across
resistor Rcomp and hence the non inverting input terminal is at ground
potential.
 Based on virtual ground concept, the voltage at node ‘a’ is zero as the non-
inverting input terminal is grounded. By applying KCL at node ‘a’, the nodal
equation is
 Hence, the output is an inverted, weighted sum of the inputs.

 If R1 = R2 = R3 = Rf, V0 = -(V1 + V2 + V3)
 If R1 = R2 = R3 = 3Rf, then
V0 = - (V1 + V2 + V3)
3
 For practical op-amp, input bias current compensating resistor Rcomp should be
used and this can be found by making all inputs V1 = V2 = V3= 0. Then,
effective input resistance,
Ri = R1║R2║R3
Therefore, Rcomp = Ri║Rf = R1║R2║R3║Rf
Ex:
Design an adder circuit using an op-amp to get the output expression as
V0 = - (0.1 V1 + V2 + 10 V3)
Non-inverting Summing Amplifier
Non-inverting Summing Amplifier
• The nodal equation at node ‘a’ is
• Based on virtual ground concept, the voltage at inverting input can be taken as
the voltage at node ‘a’ i.e. Va
Therefore, the output voltage is a non-inverted weighted sum of inputs,
Let R1 = R2 = R3 = R = Rf/2, then V0 = V1 + V2 + V3

Subtractor
 A basic differential amplifier can be used as a subtractor by taking all

resistor values as same.
 Now the output voltage can be obtained by using superposition principle.
Subtractor
 If V2 = 0, the circuit becomes a non-inverting amplifier having input voltage
V1/2 at the non-inverting input terminal and the output voltage V01 becomes
 If V1 = 0, the circuit becomes an inverting amplifier and output voltage V02 is
V02 = -V2
 Finally the output voltage V0 due to both the inputs can be written as
V0 = V01 + V02 = V1 – V2
Adder-Subtractor
 The output voltage V0 can be obtained by using superposition principle.

 The output voltage V01 due to V1 alone can be obtained by making all other
source voltages V2 = V3 = V4 = 0
Adder-Subtractor
Thevenin’s equivalent
 The circuit becomes an inverting amplifier and output voltage is
 Similarly, the output voltage V02 due to V2 alone is,

V02 = - V2
Adder-Subtractor
 Now, the output voltage due to input voltage V3 alone by making other
voltages V1 = V2 = V4 = 0. Now the circuit becomes non-inverting
amplifier.
 The voltage Va at the non-inverting terminal is

Adder-Subtractor
 So, the output voltage V03 due to V3 alone is
 Similarly, the output voltage V04 due to V4 alone is,
V04 = V4
 The output voltage V0 due to all four input voltages is given by
V0 = V01 + V02 + V03 + V04

= – V1 – V2 + V3 + V4
V0 = (V3 + V4) – (V1 + V2)
Instrumentation Amplifier
 An Instrumentation amplifier is an integrated circuit (IC) used to amplify a
signal, which is a type of differential amplifier because it amplifies between two

input signals.
 In many industrial and consumer applications, it is required to measure
physical quantities like temperature, light intensity, water flow, etc.
 These physical quantities are usually measured with the help of transducers
and the output of transducer has to be amplified so that it can drive the
indicator or display system.
 So, for amplifying the transducer output signals of low amplitude, we will go
for specially designed instrumentation amplifier.

 The important features of an instrumentation amplifier are:
 High gain accuracy
 High CMRR
 High gain stability with low temperature coefficient
 Low dc offset
 Low output impedance
 These are specially designed op-amps such as μA725 to meet above
requirements.
 Monolithic instrumentation amplifier are also available – AD521, AD524,
AD260, AD624 by Analog Devices, LM-363.XX(XX – 10,100,500) by

National Semiconductor and INA101,104, 3626, 3629 by Burr-Brown.
The output voltage V0 for above differential amplifier is given by,

For R1/R2 = R3/R4,
 In the circuit of differential amplifier,

the source V1 sees an input impedance = R3 + R4 =101 kΩ and
the source V2 sees an input impedance = R1 = 1 kΩ
 This low impedance may load the signal source heavily and
therefore, a high resistance buffer is used preceding each input to
avoid this loading effect.
 The op-amps A1 and A2 have differential input voltage as zero.

 For V1 = V2 i.e. under common mode condition, the voltage across R will be
zero.
 As no current flows through R and R’, both non-inverting amplifiers A1 and A2
acts as voltage followers and their output voltages equal to input voltages i.e.
V2’ = V2 and V1’ = V1.
 However, if V1 ≠ V2, current flows in R and R’ and (V2’ - V1’ )> (V2 - V1).
 Therefore, this circuit has differential gain and CMRR more compared to the
single op-amp circuit.
 The output voltage V0 can be calculated using superposition theorem,
 Since no current flows into op-amp, the current I flowing upwards in R is

I = (V1 – V2)/R and passes through the resistor R’.
Substitute these values in output voltage V0 equation,

 In above equation, if we choose R2 =R1 =25 kΩ and R’ = 25 kΩ and R =50
Ω then a gain of (1+(2*(25k Ω /50 Ω))) = 1001 can be achieved.
 This difference gain of this instrumentation amplifier can be varied by
replacing the resistance R by a potentiometer.
 The resistance R however should never be made zero, as this will make
the gain infinity.
 To avoid this situation, in a practical circuit, a fixed resistance in series
with a potentiometer is used in place of R.

Applications of Instrumentation Amplifier
 Strain gauge bridge interface for pressure and temperature sensing.
 A variety of low side and high side current sensing application
 Medical instrumentation, used in ECG connection
 Current/voltage monitoring
 Audio application involving weak audio signal
 High speed signal conditioning
 Temperature indicator and temperature controller
 Light intensity meter, etc.

Sample and Hold circuit using op-amp
 A sample and hold circuit samples an input signal and holds on to its last
sampled value until the input is sampled again.
 This type of circuit is very useful in digital interfacing and analog to digital and
pulse code modulation systems.
 From the figure, the n-channel E-MOSFET works as a switch and is
controlled by the control voltage vc and the capacitor C stores the charge.
 The analog signal vi to be sampled is applied to the drain of E-MOSFET and
the control voltage vc is applied to its gate.
 When vc is positive, the E-MOSFET turns on and the capacitor C charges to the
instantaneous value of input vi with a time constant (R0 + rDS(on))*C.
 Here R0 is the output resistance of the voltage follower A1 and rDS(on)
is the resistance of the MOSFET when on.
 Thus the input voltage vi appears across the capacitor C and then at the output
through the voltage follower A2.

 From the waveforms, during the time when control voltage vc is zero, the E-
MOSFET is off.
 The capacitor C is now facing the high input impedance of the voltage follower
A2 and hence cannot discharge. So, the capacitor holds the voltage across it.
 The time period TS, the time during which voltage across the capacitor is equal
to input voltage is called sample period.
 The time period TH of vc during which voltage across the capacitor is held
constant is called hold period.
 The frequency of the control voltage should be kept higher than (at least twice)
the input so as to retrieve the input from output waveform.
 A low leakage capacitor such as Polystyrene, Mylar, or Teflon should be used to
retain the stored charge.

Multipliers and Dividers
Analog Multiplier:
 There are a number of applications of analog multipliers such as
i) frequency doubling
ii) measurement of real power
iii) detecting phase-angle difference between two signals of equal

frequency
iv) multiplying two signals
v) dividing one signal by another
vi) taking square root of a signal
vii) squaring a signal

 From the basic multiplier schematic symbol, there are two signal inputs
(vx and vy) are provided.
 The output is the product of the two inputs divided by a reference voltage Vref.
 Thus output voltage is a scaled version of x and y inputs.
 The output voltage is given by
 Normally, Vref is internally set to 10 volts. So,
 As long as vx < Vref and vy < Vref, the output of the multiplier will not
saturate.
 Power supply voltage can range from ±8 V to ±18 V, usually ±15 V.
 If both inputs are positive, the IC is said to be a one quadrant multiplier.
 A two quadrant multiplier will function properly if one input is held positive
and other is allowed to swing both positive and negative.
 If both inputs may be either positive or negative, the IC is called a four
quadrant multiplier.
 There can be several ways to make a circuit which will multiply

according to above equation.
 One commonly used technique is log-antilog method.
 The log-antilog method relies on the mathematical relationship that the
sum of the logarithm of two numbers equals the logarithm of the
product of those numbers.
ln vx + ln vy = ln (vx vy)
 Log-amps require the input and reference voltages to be of same polarity.
 This restricts log-antilog multipliers to one quadrant operation.
 A technique that provides four quadrant multiplication is transconductance

multiplier.
 Some of the multiplier IC chips available are AD533, AD534, AD633
Frequency Doubling:
 The multiplication of two sine waves of the same frequency , but of possibly
different amplitudes and phase allows to double a frequency and to directly
measure real power.
Let vx = Vx sin ωt
vy = Vy sin (ωt + θ)
where θ is the phase difference between the two signals.
Frequency Doubling
 The first term is a DC and is set by the magnitude of the signals and their phase
difference.
 The second term varies with time, but at twice the frequency of the inputs (2ω).
 The circuit works as an ideal doubler if same frequency is applied to both the
inputs. For example, if
Frequency Doubling
 The output thus contains a dc term and a negative cosine wave of
double frequency.
 The dc term can be easily removed by using a 1 μF coupling capacitor
between load and the output terminal.

Squarer Circuit
 The basic multiplier can be used to square any positive or negative

number provided the number can be represented by a voltage between
0 to Vref.
 The voltage vi representing the number is connected to both the inputs.
Squarer Circuit
 It is possible to square a sine wave too. If a sine wave voltage vi = Vm sin

ωt is applied to both the inputs, then the output voltage, v0 is given by
 The output contains a dc term and frequency is doubled.

Divider
 Division, the complement of multiplication, can be accomplished by placing the

multiplier circuit element in the op-amp’s feedback loop.
 The output voltage from the divider with input signals vz and vx as dividend and
divisor respectively, is given by
Divider
 The op-amp’s inverting terminal is at virtual ground. Therefore,

Iz = IA
and Iz = vz / R
 The output voltage VA of the multiplier is determined by the
multiplication of vx and vy
Finding Square Roots
 Multiplier IC can be used for squaring a signal. Similarly, divider circuit

can be used to take the square root of a signal.
 A divider circuit can be used to find square roots by connecting both
the inputs of the multiplier to the output of an op-amp.
Finding Square Roots
(Taking magnitude only in above equation)
 Thus, the output V0 is proportional to square root of magnitude of Vin.

 Note that Vin must be negative or else op-amp will saturate.
 The rate of Vin lies between -1 and -10 V.
Differentiator
 As the name suggests, the circuit performs the mathematical operation

of differentiation, that is, the output waveform is the derivative of input
waveform.
Differentiator
 From the figure, the node N is at virtual ground potential i.e., vN = 0.

 The current iC through the capacitor is,
 The current if through the feedback resistor is v0/Rf and there is no current
into the op-amp. Therefore, the nodal equation at N is,
 Thus, the output voltage v0 is a constant (-RfC1) times the derivative of the
input voltage vi and the circuit is a differentiator.
 The minus sign indicates a 180◦ phase shift of the output waveform v0 with
respect to the input signal.
Differentiator
 The phasor equivalent of above equation is, V0(s) = -RFC1 s Vi(s)

Where V0 and Vi are the phasor representation of v0 and vi.
 In steady state, put s =jω and then the magnitude of gain A of the
differentiator as,
 It can be written as
 At f = fa, |A| = 1, i.e. 0 dB, and the gain increases at a rate of +20 dB/dec.
 Thus at high frequency, a differentiator may become unstable and break into
oscillations.
 There is one more problem i.e., the input impedance (i.e. 1/ ω C1) decreases
with increase in frequency, thereby making the circuit sensitive to high
frequency noise.
Practical Differentiator
 A practical differentiator eliminates the problem of instability and high

frequency noise.
 The transfer function for the circuit is given by,

 For RFCF = R1C1,
 From the equation, it is evident that the gain increases at +20 dB/dec for
frequency f < fb and decreases at -20 dB/dec for f > fb as shown by dashed
lines in the plot.
 This 40 dB/dec change in gain is caused by R1C1 and RFCF factors.
 For the basic differentiator, the frequency response would have increased
continuously at the rate of +20 dB/dec even beyond fb causing stability
problem at high frequency.
 Thus the gain at high frequency is reduced significantly, thereby avoiding the
high frequency noise and stability problems.
 The value of fb should be selected such that fa < fb < fc

Where fc is the unity gain-bandwidth of the op-amp in open loop configuration
 For good differentiation, one must ensure that the time period T of the input
signal is larger than or equal to RFC1, i.e., T >= RFC1
 It may be noted that for RFC1 much greater than R1C1 or RFCF,
V0/Vi = -sRFC1 i.e., the expression of the output voltage remains the
same as in the case an ideal differentiator as
 A resistance Rcomp = R1||RF is normally connected to the (+) input terminal

to compensate for the input bias current.
 A good differentiator may be designed as per the following steps:
i) Choose fa equal to the highest frequency of the input signal. Assume a
practical value of C1 (<1μf) and then calculate R1
ii) Choose fb = 10 fa (say). Now calculate the values of R1 and C1 so that
R1C1 = RFCF
Integrator
 Integrator circuit can be obtained by interchanging the resistor and

capacitor of the differentiator.
 The nodal equation at node N is,

Integrator
 The circuit, thus provides an output voltage which is proportional to the time
integral of the input and R1CF is the time constant of the integrator.
 It may be noted that there is negative sign in the output voltage and therefore,
this integrator is also known as inverting integrator.
 A resistance Rcomp = R1 is usually connected to the (+) input terminal to
minimize the effect of input bias current.
 A simple low pass RC circuit can also work as an integrator when time constant
is very large i.e., it requires very large values of R and C.
Integrator
 The components R and C cannot be made infinitely large because of practical

limitations.
 However, in the op-amp integrator of figure, by Miller’s theorem, the effective
input capacitance becomes CF (1-Av) where Av is the gain of the op-amp.
 The gain Av is infinite for an ideal op-amp, so the effective time constant of the
op-amp integrator becomes very large which results in perfect integration.
 The operation of the integrator can also be studied in the frequency domain. In
phasor notation, it can be written as
Integrator
 The frequency response (or Bode plot) of this basic integrator is shown below.
 The Bode plot is a straight line of slope -6dB/octave.
Integrator
 The frequency fb in plot, is the frequency at which the gain of the integrator is
0 dB and is given by
 It can further be seen from magnitude |A| equation that at ω = 0, the

magnitude of the integrator transfer function is infinite.
 At dc, the capacitor CF behaves as an open circuit and there is no negative
feedback.
 The op-amp thus operates in open loop, resulting in an infinite gain.
 In practice, output never becomes infinite, rather the output of the amplifier
saturates at a voltage close to the op-amp positive or negative power supply
depending on the polarity of the input dc signal.
 As the gain of the integrator decreases with increasing frequency, the integrator
circuit does not have any frequency problem as faced in a differentiator.
 However, at low frequencies such as at dc (ω = 0), the gain becomes infinite (or
saturates).
Practical Integrator (Lossy integrator)
 The gain of an integrator at low frequency (dc) can be limited to avoid the
saturation problem if the feedback capacitor is shunted by a resistance R.
 The parallel combination of RF and CF behaves like a practical capacitor which
dissipates power unlike an ideal capacitor.
 For this reason, this circuit also called a lossy integrator.
 The resistor RF limits the low frequency gain to –RF/R1 (generally RF=10*R1)
and thus provides dc stabilization.
Practical Integrator
 The nodal equation at the inverting input terminal of op-amp is,
 If RF is large, the lossy integrator approximates the ideal integrator.

 For s= jω, magnitude of the gain of lossy integrator is given by
 From the plot, at low frequencies gain is constant at RF/R1.

 The break frequency (f = fa) at which the gain is 0.707 (RF/R1) is calculated
from
Practical Integrator
 Solving for f = fa, we get
 This is very important frequency. It tells us where the useful integration

range starts.
 If the input frequency is lower than fa the circuit acts like a simple inverting
amplifier and no integration results.
 At input frequency equal to fa, 50% accuracy results.
 The practical thumb rule is that if the input frequency is 10 times fa, than
99% accuracy can result.
DC Characteristics of Op-Amp
 An ideal op-amp draws no current from the source and its response is also
independent of temperature.
 However, in a practical op-amp, the current is taken from the source into the
Op-amp inputs.
 Also the two inputs respond differently to current and voltage due to
mismatch in transistors.
 A real op-amp also shifts its operation with temperature.
 These non ideal dc characteristics that add error components to the dc
output voltage are:
• Input bias current
• Input offset current
• Input offset voltage
• Thermal drift
DC Characteristics of Op-Amp
 Input bias current:

 The op-amp’s input is a differential amplifier, which may be made of
BJT or FET.
 In either case, the input transistors must be biased into their linear
region by supplying currents into the bases by the external circuit.
 In an ideal op-amp, we assumed that no current is drawn from the
input terminals.
 However, practically, input terminals takes a small value of dc current
to bias the input transistors.
 The base currents entering into the inverting and non-inverting
terminals are shown as IB- and IB+ respectively.
 Even though both the transistors are identical, IB- and IB+ are not
exactly equal due to internal imbalances between the two inputs.
Input bias current
 Manufacturers specify input bias current IB as the average value of the

base currents entering into the terminals of an op-amp.
Input bias current
 For 741, a bipolar op-amp, the bias current is 500nA or less.

 The FET input op-amp will have bias currents as low as 50pA at room
temperature.
 Consider the basic inverting amplifier, if input voltage Vi is set to zero volt,
the output voltage V0 should also be zero volt. But the output voltage due
to bias current is
V0 = (IB- )Rf
 For a 741 op-amp, with a 1 MΩ feedback resistor,
V0 = 500n * 1M = 500mV
 The output is driven to 500mV with zero input because of the bias
currents.
 In applications where signal levels are measured in milli volts, this is totally
unacceptable.
 This effect can be compensated by using a compensating resistor Rcomp
Input bias current
By KVL at node ‘a’,

-V1 + V2 - V0 = 0
V0 = V2 – V1
Input bias current
 By selecting proper value of Rcomp, the V2 can be cancelled with V1 and

the output V0 will become zero.
 The voltage at node ‘a’ is (-V1), because the voltage at the non-inverting
input terminal is (-V1). So, with Vi = 0, we get
 As, V0 = V2 – V1, for compensation V0 should be zero for Vi = 0 i.e. V2 = V1

Input bias current
KCL at node ‘a’ gives
Assuming IB- = IB+

Input bias current
 The effect of input bias current in a non-inverting amplifier can also be

compensated by placing a compensating resistor Rcomp in series with the
input signal Vi
Input offset current
 Bias current compensation will work if both bias currents IB- and IB+
are equal.
 Since the input transistors cannot be made identical, there will always
be some small difference between IB- and IB+
 This difference is called the offset current Ios and can be written as
|Ios| = IB+ - IB-
 The absolute value sign indicates that there is no way to predict which
of the bias currents will be larger.
 Offset current for BJT op-amp is 200 nA and that for FET op-amp is
10 pA.
 Even with bias current compensation, offset current will
produce an output voltage when the input voltage Vi is zero
Input offset current
 KCL at node ‘a’ gives,
 So, even with bias current compensation and with the feedback resistor
of 1 MΩ , a 741 BJT op-amp has an output offset voltage
V0 = 1 M * 200 n = 200 mV with zero input
Input Offset Voltage
 Even after using compensating techniques, it is found that the output

voltage may still not be zero with zero input voltage.
 This is due to unavoidable imbalances inside the op-amp and one may
have to apply a small voltage at the input terminals to make output
voltage zero.
 This is the voltage required to be applied at the input for making output
voltage to zero volts.
 The voltage V2 at the (-) input terminal is given by

Total Output Offset Voltage
 The maximum offset voltage at the output of an inverting and non-

inverting amplifier without any compensating technique used, is given
by
 With Rcomp, the total output offset voltage will be

Offset null pin connection for μA741 Balancing circuit for inverting amplifier
Balancing circuit for non-inverting amplifier

Thermal Drift
 Bias current, offset current and offset voltage change with temperature.
 A circuit carefully nulled at 25◦C may not remain so when the temperature
rises to 35◦C. This is called drift.
 Often, offset current drift is expressed as nA/ ◦C and offset voltage
drift in mV/ ◦C.
 These indicate the change in offset for each degree Celsius change in
temperature.
 There are very few circuit techniques that can be used to minimize the
effect of drift.
• Careful printed circuit board layout must be used to keep op-amp
away from source of heat.
• Forced air cooling may be used to stabilize the ambient temperature.
AC Characteristics of Op-Amp
Frequency Response:
 Ideally, an op-amp should have infinite bandwidth. This means that, if its
open-loop gain is 90dB with dc signal its gain should remain the same 90dB
through audio and on to high radio frequencies.
 The practical op-amp gain, however decreases (rolls-off) at higher frequencies.
 Which component is responsible for above problem? Obviously there must be a

capacitive component in the equivalent circuit of the op-amp.
 This capacitance is due to the physical characteristics of the device (BJT or
FET) used and the internal construction of op-amp.
 For an op-amp with only one break (corner) frequency , all the capacitor effects
can be represented by a single capacitor C .
 The high frequency model of op-amp is nothing but a modified version of the
low frequency model with a capacitor C at the output.
Frequency Response
There is one pole due to R0C and obviously one -20dB/dec roll-off comes into effect.
Frequency Response
 Where f1 is the corner frequency or the upper 3 dB frequency of the op-amp.

 The magnitude and the phase angle of the open loop voltage gain are function
of the frequency and can be written as
Frequency Response
Frequency Response
 From the magnitude plot, it can be seen that,

 For frequency f << f1, the magnitude of the gain is 20 logAOL in dB
 At frequency f=f1, the gain is 3 dB down from the dc value of AOL in dB.
This frequency f1 is called corner frequency.
 For f >> f1, the gain rolls-off at the rate of -20dB /dec (or) -6dB/octave.
 From the phase plot, it can be seen that,

 The phase angle is zero at frequency f = 0 Hz.
◦
 At corner frequency f1, the phase angle is -45 (lagging)
◦
 At infinite frequencies, the phase angle is -90 which is maximum
phase angle with a single capacitor.

 The voltage transfer function in s-domain can be written as
Frequency Response
 A practical op-amp, however, has number of stages and each stage produces a
capacitive component.
 Thus due to RC pole pairs, there will be a number of different break
frequencies.
 The transfer function of an op-amp with three break frequencies can be
written as
Frequency Response
Frequency Response
 From the plot, the open loop frequency response is flat (90dB) from low
frequencies (including dc) to 200 kHz, the first break frequency.
 From 200 kHz to 2 MHz, the gain drops from 90dB to 70dB which is at a
-20 dB/dec or -6 dB/octave rate.
 From 2 MHz to 20 MHz, the roll-off rate is -40 dB/dec or -12 dB/octave.
 Accordingly, as frequency is increasing, the cascading effect of RC pairs (poles)
come into effect and roll-off rate increases successively by -20 dB/dec at each
corner frequency.
 Each RC pole pair also introduces a lagging phase of maximum up to -90◦

Slew Rate
 The rise time of an amplifier is defined as the time the output takes to change
from 10% to 90% of the final value for a step input and is given as
tr = 0.35/BW
 Ideal response time should be zero seconds as BW is infinite for ideal op-amp,
that is, output voltage should respond instantaneously to any change in the
input.
 For small signals (Vm < 1 volt), the rise time is specified and for large signals
output, the op-amp’s speed is limited by the slew rate.
 Usually op-amps with wide bandwidth will have higher (better) slew rates.
 The slew rate is defined as the maximum rate of change of output voltage
caused by a step input voltage and is usually specified in V/μs.
Contd...
Slew Rate
 An ideal slew rate is infinite which means that op-amp’s output voltage should
change instantaneously in response to input step voltage.
 Practical IC op-amps have specified slew rates from 0.1 V/μs to well above
1000 V/μs.
 The slew rate improves with higher closed loop gain and dc supply voltage and
slew rate decreases with an increase in temperature.
 There is usually a capacitor within or outside an op-amp to prevent oscillation
and this capacitor which prevents the output voltage from responding
immediately to a fast changing input.
Slew Rate
 For 741C, the slew rate is
Consider a voltage follower,

If vs = Vm sin wt
then output vo = Vm sin wt
Slew Rate
 The rate of change of the output is given by
 The maximum rate of change of the output occurs when cos wt = 1.
 Therefore,
 Slew rate = 2πfVm volt/sec
Where, f = input frequency in Hz

Vm = peak output amplitude in volts
Slew Rate
 If 2πfVm /106 less than the slew rate of op-amp, then output will be
undistorted.
 If frequency or amplitude of input signal is increased to exceed slew rate of op-
amp, the output will be distorted.
 The maximum input frequency fmax at which we can obtain an undistorted
output voltage of peak value Vm is given by
 It is also called full power response. It is the maximum frequency of a large
amplitude sine wave with which op-amp can have without distortion.
Comparators
 An op-amp in the open loop configuration operates in a non-linear

manner.
 There are a number of applications of op-amp in this mode, such as
comparators, detectors, limiters and digital interfacing devices namely
converters.
 A comparator is a circuit which compares a signal voltage applied at
one input of an op-amp with a known reference voltage at the other
input.
 It is basically an open-loop op-amp with output ± Vsat ( =VCC)
Comparators
Comparators
 It may be seen that the change in the output state takes place with an
increment in input vi of only 2 mV.
 This is the uncertainty region where output cannot be directly defined.
 This region is due to input offset-voltage and it can be eliminated by
using off-set null compensating techniques.
 There are basically two types of comparators:
i) Non –inverting comparator
ii) Inverting comparator
Non-inverting comparator:
 A fixed reference voltage Vref is applied to (-) input terminal and a time
varying signal vi is applied to (+) input.
 The output voltage is at –Vsat for vi < Vref and
v0 goes to +Vsat for vi > Vref.
Non-inverting comparator
Vref positive Vref negative

 In a practical circuit Vref is obtained by using 10 kΩ potentiometer

which forms a voltage divider with the supply voltages V+ and V- with
the wiper connected to (-) input terminal.
 Thus a Vref of desired amplitude and polarity can be obtained by simply
adjusting the 10 kΩ potentiometer.
Inverting comparator
 In practical inverting comparator, the reference voltage Vref is applied

to the (+) input and vi is applied to (-) input.
Inverting comparator
Comparators
 Output voltage levels independent of power supply voltages can also be

obtained by using a resistor R and two back to back zener diodes at the output
of op-amp.
 The value of resistance R is chosen so that for the zener diodes operate at the
recommended current.
 It can be seen that the limiting voltages of v0 are (VZ1 + VD) and – (VZ2 + VD)
where VD (~0.7V) is the diode forward voltage.
Comparators
 In the waveforms, the output transitions are shown as taking place

instantaneously.
 Practical circuits, however take a certain amount of time to switch from one
voltage level to another.
 The actual waveform will therefore exhibit slanted edges as well as delays at the
points of input threshold crossing.
 These effects are more noticeable at high frequencies where the output
switching times are comparable or even longer than the input period itself.
 Thus there is an upper limit to the operating frequency of any comparator.
 If 741, the internally compensated op-amp is used as comparator, the primary
limitation is the slew rate.
 Since 741C has slew rate of 0.5 V/μs, it takes 2 * 13/0.5 ≈ 50 μs (Vsat =
±13V for 741) to swing from one saturation level to the other.
 In many applications, this is too long. To decrease the response time, it is
possible to use uncompensated op-amps such as 301 for comparator
applications.
Regenerative Comparator (Schmitt Trigger)
 If positive feedback is added to the comparator circuit, gain can be increased

greatly.
 Consequently, the transfer curve of comparator becomes more close to ideal
curve.
 Theoretically, if the loop gain –βAOL is adjusted to unity, then the gain with
feedback, AVf becomes infinite.
 This results in an abrupt (zero rise time) transition between the extreme values
of output voltage.
 In practical circuits, however, it may not be possible to maintain loop-gain
exactly equal to unity for a long time because of supply voltage and
temperature variations.
 So, a value greater than unity is chosen. This also gives an output waveform
virtually discontinuous at the comparison voltage.
 This circuit, however, now exhibits a phenomenon called hysteresis or
backlash.
Schmitt Trigger
 The input voltage is applied to the (-) input terminal and feedback voltage to
the (+) input terminal.
 The input voltage vi triggers the output v0 every time it exceeds certain voltage
levels.
 These voltage levels are called upper threshold voltage (VUT) and lower threshold
voltage (VLT).
Schmitt Trigger
 The hysteresis width is the difference between these two threshold

voltages i.e. VUT – VLT.
 These threshold voltages are calculated as follows:
 Suppose the output v0 = + Vsat. The voltage at (+) input terminal can
be obtained by using superposition
 This voltage is called upper threshold voltage VUT.

 As long as vi < VUT, the output v0 remains constant at +Vsat.
 When vi is just greater than VUT, the output regeneratively switches
to –Vsat and remain at this level as long as vi >VUT.
 For v0 = -Vsat, the voltage at (+) input terminal is,
Schmitt Trigger
Schmitt Trigger
 The input voltage vi must become lesser than VLT in order to cause v0 to
switch from – Vsat to +Vsat.
 A regenerative transition takes place as shown waveform (c) and the output v0
returns from – Vsat to + Vsat almost instantaneously.
 Note that VLT < VUT and the difference between these two voltages is the
hysteresis width VH and can be written as
 Because of the hysteresis, the circuit triggers at a higher voltage for increasing
signals than for decreasing ones.
 Further, note that if peak to peak input signal vi were smaller than VH then the
Schmitt trigger circuit, having responded at a threshold voltage by a transition
in one direction would never itself, that is, once the output has jumped to, say,
+Vsat it would remain at this level and never return to –Vsat.
 It may be seen from above equation that VH is independent of Vref
Schmitt Trigger
 The resistor R3 in circuit is chosen equal to R1||R2 to compensate for

the input bias current.
 A non-inverting Schmitt trigger is obtained if vi and Vref are
interchanged.
 The most important application of Schmitt trigger circuit is to convert a
very slowly varying input voltage into a square wave output.
Schmitt Trigger
 If Vref is chosen as zero volt, then
 If an input sinusoid of frequency f = 1/T is applied to such a comparator, a

symmetrical square wave is obtained at the output.
 The vertical edge of the output waveform however, will not occur at the time
the sine wave passes through zero but is shifted in phase by θ where sin θ =
VUT/Vm and Vm is the peak sinusoidal voltage.
 Special purpose Schmitt triggers are commercially available.
 T1-13, T1-14 and T1-132 chips with totem pole output and VUT = 1.7V, VLT
= 0.9V are available.
 The T1-132 package is a quad two-input NAND Schmitt trigger.
 CMOS Schmitt triggers offer the advantage of high input impedance and low
power consumption.
 Examples of CMOS inverting Schmitt trigger are CD40106B and 744C14.
Schmitt Trigger
Schmitt Trigger
 An interesting application of hysteresis is in the detection and counting of the

zero crossings of an arbitrary waveform if it is superimposed with interference
say of a frequency much higher than the signal.
 From the figure, the clean signal crosses the zero axis a number of times when
corrupted with noise interference around each of the zero crossings points we
are trying to detect.
 A simple comparator would change state at each of the zero crossings.
 If, however, we know the expected peak to peak amplitude of the interference,
the problem is solved by introducing the hysteresis of appropriate width in the
circuit as shown by VUT and VLT in fig.
 The hysteresis in the comparator characteristics thus provides an effective
means of rejecting interference.
Schmitt Trigger
Illustrating the use of hysteresis in the comparator characteristics as a means of

rejecting noise
Square Wave Generator (Astable Multivibrator)
 A square wave generator is also called a free running oscillator, the principle of
generation of square wave output is to force an op-amp to operate in the
saturation region.
Astable Multivibrator
 In the circuit, Va = v0 *(R2/(R1 + R2)) = v0*β

Where β = R2/(R1 + R2) is a fraction and this fraction of output is fed
back to the (+) input terminal.
 Thus the reference voltage Vref = β*v0 and may take values as
+βVsat or -βVsat .
 The output is also fed back to the (-) input terminal after integrating by
means of a low-pass RC combination.
 Whenever input at the (-) input terminal just exceeds Vref,
switching takes place resulting in a square wave output.
 In astable multivibrator, both the states are quasi stable.
 Consider an instant of time when the output is at +Vsat.
 The capacitor now starts charging towards +Vsat through
resistance R, as shown in waveform.
 The voltage at the (+) input terminal is held at +βVsat by R1 and R2

combination.
 This condition continues as the charge on C rises, until it has just
exceeded +βVsat, the reference voltage.
 When the voltage at the (-) input terminal becomes just greater than
this reference voltage, the output is driven to –Vsat.
 At this instant, the voltage on the capacitor is +βVsat and it begins to
discharge through R, i.e., charges toward –Vsat.
 When the output voltage switches to –Vsat, the capacitor charges more
and more negatively until its voltage just exceeds –βVsat.
 The output switches back to +Vsat and the cycle repeats itself.
 The frequency is determined by the time it takes the capacitor to charge
from –βVsat to +βVsat and vice versa.
 The voltage across the capacitor as a function of time is given by,
vc(t) = Vf + (Vi – Vf) e-t/RC
where, the final value, Vf = +Vsat
and the initial value, Vi = –βVsat

 Therefore,
vc(t) = Vsat + ( –βVsat – Vsat) e-t/RC
vc(t) = Vsat – Vsat (1+β) e-t/RC

 At t = T1, voltage across the capacitor reaches βVsat and switching
takes place. Therefore,
vc(T1) = βVsat = Vsat – Vsat (1+β) e-t/RC
 This give only one half of the period. Total time period is,
and the output waveform is symmetrical.

 If R1 = R2, then β = 0.5, and T = 2*RC*ln 3. And for R1= 1.16*R2,
it can be seen that T= 2*RC
 The output swings from +Vsat to –Vsat, so,

v0 (peak to peak) = 2*Vsat
 The peak to peak output amplitude can be varied by varying the power
supply voltage.
Monostable Multivibrator
 Monostable multivibrator has one stable state and the other is quasi
stable state.
 The circuit is useful for generating single output pulse of adjustable
time duration in response to a triggering signal.
 The width of the output pulse depends only on external components
connected to the op-amp.
 The circuit for monostable multivibrator is a modified version of the
astable multivibrator.
 A diode D1 clamps the capacitor voltage to 0.7V when the output is at
+Vsat.
 A negative going pulse signal of magnitude V1 passing through the
differentiator R4C4 and diode D2 produces a negative going triggering
impulse and is applied to the (+) input terminal.
 To analyse the circuit, let us assume that in the stable state, the output
v0 is at +Vsat.
 The diode D1 conducts and vc the voltage across the capacitor C gets
clamped to +0.7V.
 The voltage at the (+) input terminal through R1 R2 potentiometric
divider is + βVsat .
 Now, if a negative trigger of magnitude V1 is applied to the (+) input
terminal so that the effective signal at this terminal is < 0.7V, i.e.
([βVsat + (-V1)] < 0.7V), the output of the op-amp will switch from
+Vsat to –Vsat.
 The diode will now get reverse biased and the capacitor starts charging
exponentially to –Vsat through the resistance R.
 The voltage at the (+) input terminal is now –βVsat.
 When the capacitor voltage vc becomes just slightly more negative than
–βVsat, the output of the op-amp switches back to +Vsat.
 The capacitor C now starts charging to +Vsat through R until vc is 0.7V
as capacitor C gets clamped to the voltage.
 The pulse width T of monostable multivibrator is calculated as follows:
The general solution for a single time constant low pass RC circuit with
V1 and Vf as initial and final values is
v0 = Vf + (Vi – Vf) e-t/RC
For the circuit, Vf = –Vsat and Vi = VD (diode forward voltage), the

output vc is
vc = –Vsat + (VD + Vsat) e-t/RC
at t =T,
vc = –βVsat
 Therefore, –βVsat = –Vsat + (VD + Vsat) e-T/RC
 From this, pulse width T is obtained as
where β = R2/(R1 + R2)

 If, Vsat >>VD and R1 = R2 so that β =0.5, then
T = 0,69* RC
 For monostable operation, the trigger pulse width Tp should be much less
than T, the pulse width of the monostable multivibrator.
 The diode D2 is used to avoid malfunctioning by blocking the positive noise
spikes that may be present at the differentiated trigger input.
 It may be noted that from waveforms, that capacitor voltage vc reaches its
quiescent values VD at T’ > T.
 Therefore, it is essential that a recovery time T’ – T be allowed to
elapse before the next triggering signal is applied.
 The circuit can be modified to achieve voltage to time delay conversion
as in the case of square wave generator.
 The monostable multivibrator circuit is also referred to as time delay
circuit as it generates a fast transition at a predetermined time T after

the application of input trigger.
 It is also called a gating circuit as it generates a rectangular waveform
at a definite time and thus could be used to gate parts of a system.

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LINEAR AND DIGITAL

 Hence, the output is an inverted, weighted sum of the inputs.

Therefore, Rcomp = Ri║Rf = R1║R2║R3║Rf

• The nodal equation at node ‘a’ is

Therefore, the output voltage is a non-inverted weighted sum of inputs,

Let R1 = R2 = R3 = R = Rf/2, then V0 = V1 + V2 + V3

 A basic differential amplifier can be used as a subtractor by taking all

 If V2 = 0, the circuit becomes a non-inverting amplifier having input voltage

 If V1 = 0, the circuit becomes an inverting amplifier and output voltage V02 is

 The output voltage V0 can be obtained by using superposition principle.

 The circuit becomes an inverting amplifier and output voltage is

 Similarly, the output voltage V02 due to V2 alone is,

 The voltage Va at the non-inverting terminal is

 So, the output voltage V03 due to V3 alone is

 Similarly, the output voltage V04 due to V4 alone is,

V0 = V01 + V02 + V03 + V04

 An Instrumentation amplifier is an integrated circuit (IC) used to amplify a

signal, which is a type of differential amplifier because it amplifies between two

 In many industrial and consumer applications, it is required to measure

physical quantities like temperature, light intensity, water flow, etc.

for specially designed instrumentation amplifier.

 The important features of an instrumentation amplifier are:

 High gain accuracy

 High gain stability with low temperature coefficient

 Low output impedance

 These are specially designed op-amps such as μA725 to meet above

 Monolithic instrumentation amplifier are also available – AD521, AD524,

AD260, AD624 by Analog Devices, LM-363.XX(XX – 10,100,500) by

The output voltage V0 for above differential amplifier is given by,

For R1/R2 = R3/R4,

 In the circuit of differential amplifier,

 The op-amps A1 and A2 have differential input voltage as zero.

 Since no current flows into op-amp, the current I flowing upwards in R is

Substitute these values in output voltage V0 equation,

 In above equation, if we choose R2 =R1 =25 kΩ and R’ = 25 kΩ and R =50

Ω then a gain of (1+(2*(25k Ω /50 Ω))) = 1001 can be achieved.

 This difference gain of this instrumentation amplifier can be varied by

replacing the resistance R by a potentiometer.

the gain infinity.

 To avoid this situation, in a practical circuit, a fixed resistance in series

with a potentiometer is used in place of R.

 Strain gauge bridge interface for pressure and temperature sensing.

 A variety of low side and high side current sensing application

 Medical instrumentation, used in ECG connection

 Audio application involving weak audio signal

 High speed signal conditioning

 Temperature indicator and temperature controller

 Light intensity meter, etc.

 From the figure, the n-channel E-MOSFET works as a switch and is

 The analog signal vi to be sampled is applied to the drain of E-MOSFET and

the control voltage vc is applied to its gate.

instantaneous value of input vi with a time constant (R0 + rDS(on))*C.

 Here R0 is the output resistance of the voltage follower A1 and rDS(on)

is the resistance of the MOSFET when on.

through the voltage follower A2.

to input voltage is called sample period.

constant is called hold period.

the input so as to retrieve the input from output waveform.

 A low leakage capacitor such as Polystyrene, Mylar, or Teflon should be used to

retain the stored charge.

ii) measurement of real power

iii) detecting phase-angle difference between two signals of equal

iv) multiplying two signals