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Timing Behavior
Glitches/hazards and how to avoid them
FSM Partitioning
What to do when the state machine doesn’t fit!
State Machine Signaling
Introducing Idle States (synchronous model)
Four Cycle Signaling (asynchronous model)
Dealing with Asynchronous Inputs
Metastability and synchronization
resistor
A B
open C
switch D
close switch
initially
open switch
undefined
Usual solutions
1) Wait until signals are stable (by using a clock): preferable
(easiest to design when there is a clock – synchronous design)
2) Design hazard-free circuits: sometimes necessary (clock not
used – asynchronous design)
Static 0-hazard
1
Input change causes output to go from 0 to 1 to 0 0 0
Dynamic hazards
Input change causes a double change 1 1
from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0 0 0
1 1
0 0
CS 150 - Spring 2008 – Lec #22 – Signaling - 5
Static Hazards
Due to a literal and its complement momentarily taking
on the same value
Thru different paths with different delays and reconverging
May cause an output that should have stayed at the
same value to momentarily take on the wrong value
Example:
A
A
S B
F
S
S'
B
F
S'
hazard
static-0 hazard static-1 hazard
CS 150 - Spring 2008 – Lec #22 – Signaling - 6
Dynamic Hazards
Due to the same versions of a literal taking on
opposite values
Thru different paths with different delays and reconverging
May cause an output that was to change value to
change 3 times instead of once
Example: A
C
A
F B1
3
2
B B2
1
B3
C
F
hazard
dynamic hazards
CS 150 - Spring 2008 – Lec #22 – Signaling - 7
Eliminating Static Hazards
Following 2-level logic function has a hazard, e.g.,
when inputs change from ABCD = 0101 to 1101
A
AB
CD 00 01 11 10 A 1
1 A
1
1
G1 G1
\C \C 1
00 0 0 1 1 1 1 1
G3 F G3 F
\A 0 \A 0
G2 G2
D 0 D 0
01 1 1 1 1 0 10
D ABCD = 110 0 ABCD = 110 1
11 1 1 0 0
No Glitch in this case
C
10 0 0 0 0 This is the fix
B Glitch in this case
1 0 0
A 1 A 0 A 0
G1 G1 G1
\C \C 0 \C 1
1 1 1 1
G3 F G3 F G3 F
\A 0 \A 0 \A 1
G2 G2 G2
D 0 D 0 D 1
1 1 1
So:
Gate output transitions at
MOST once, low to high
Gate cannot glitch Ground
Evaluation Evaluation
A
F
Output
B
A F
Output
B
Ground
Evaluation Evaluation
A
F
Output
B
A F
Output
B
Ground
Evaluation Evaluation
A
F
Output
B
A F
Output
B
Ground
Evaluation Evaluation
A
F
Output
B
A F
Output
B
Ground
Domino Circuit
Clocked by
Evaluation
Evaluation’
trees
notC
Note A, A’ therefore
available for every DCVS Ground
output Evaluation’
Power
Use BDDs! C
Ground
Evaluation
Evaluation’ A
A F
B Output
Evaluation
Evaluation’ A
A F
B Output
Evaluation
Evaluation’ B
A Output
HG
TL•C / ST TS / ST
T02 T08 T11 T17
TS' HY FY TS'
T03 T07 T12 T16
TS / ST TL+C' / ST
FG
T04
T06 T13 T15
(TL+C')' [TS]
Communications
Clocked Signals Clocked
Subsys tem Subsys tem
Reques t
S1 S2
Data Flow provider
requester
client server
mas ter slav e
Acknow ledgement
Req
Data
Ac k
Clk
Req
Data
Wait
Clk
Slave inhibits master by asserting wait
When slave unasserts wait, master knows request has been
processed, and can latch results
1 3
Req
Data
Ack 2 4
Req 1 1
Data
Ack 2 2
CS 150 - Spring 2008 – Lec #22 – Signaling - 40
True Asynchronous Timing
Self-Timed Circuits
Uses Req/Ack signaling as described
Components can be constructed with
NO internal clocks
Input Output
Determines on its own when the Combinational
request has been processed logic
Concept of the delay line simply Req Ack
slows down the pass through of the Delay
Req to the Ack—usually matched to
the worst case delay path
Becoming MORE important for large
scale VLSI chips were global clock
distribution is a challenge
logic 1
logic 0
logic 0 logic 1
asynchronous D Q synchronized
D Q
input input
Clk
Clocked Synchronizer
Synchronous
System
Async Q0 Async Q0
D Q Input D Q D Q
Input
Clock Clock
Q1 D Q Q1
D Q
Clock Clock
In
In is asynchronous and
fans out to D0 and D1
Q0
one FF catches the
signal, one does not
Q1
inconsistent state may
be reached!
CLK