RT Level Design

 RT level design:
 Taking a high level description of a design

 Partitioning

 Coming up with an architecture

 Designing the bussing structure

 Describing and implementing various components of the

architecture
 Steps in RT level design:
 Control/Data Partitioning

 Data Part Design

 Control Part Design

Verilog Digital System Design

Z. Navabi, 2006 1
 RT Level Design
RT Level
Design

Control/data
Partitioning

Data Part Control Part

Verilog Digital System Design

Z. Navabi, 2006 2
Control/Data Partitioning
RT Level
Design

Control/data
Control/data
Partitioning
Partitioning

Data Part Control Part

Verilog Digital System Design

Z. Navabi, 2006 3
 Control/Data Partitioning

RT Level Design
DataPath Control
Reg
Flags & status
Control
Data Inputs
Opcode Outputs
Data flow
Control signals
Control
Data Outputs
Inputs

Verilog Digital System Design

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 Data Part
RT Level
Design

Control/data
Partitioning

Data
Data Part
Part Control Part

Verilog Digital System Design

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 Data Part

DataPath
Reg
Flags & status
Data Inputs
Opcode

Data flow
Control signals

Data Outputs

Verilog Digital System Design

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 Output Signals: Going

Data Part to the control part,

provide flags and
status of the data
module DataPath
(DataInput, DataOutput, Flags, Opcodes,
ControlSignals);

input [15:0] DataInputs;

output [15:0] DataOutputs; Control Signals:
output Flags, ...; Inputs to data part,
output Opcodes, ...; sent to the data
input ControlSignals, ...; components and
busses
// instantiation of data components
// ...
// interconnection of data components
// bussing specification
endmodule

 DataPath Module
Verilog Digital System Design
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 Data Part Data Component:
Shows how the
component uses its
input control
signals to perform
module DataComponent various operations
on its data inputs
(DataIn, DataOut, ControlSignals);

input [7:0] DataIn;

output [7:0] DataOut;
input ControlSignals;
// Depending on ControlSignals
// Operate on DataIn and
// Produce DataOut
endmodule

 Partial Verilog Code of a Data Component

Verilog Digital System Design

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 Control Part
RT Level
Design

Control/data
Partitioning

Data Part Control Part

Control Part

Verilog Digital System Design

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 Control Part
Control

Flags & status

Control
Opcode Outputs
Data flow
Control signals
Control
Inputs
Makes decisions as
Consists of one or
to when and what
more state machines
control signals to
to keep the state of
issue depending on
the circuit.
its state.
Verilog Digital System Design
Z. Navabi, 2006 10
 Control Part
module ControlUnit
(Flags, Opcodes, ExternalControls, ControlSignals);

input Flags, ...; Takes control

input Opcodes, ...; inputs from the
input ExternalControls, ...; Data Part
output ControlSignals;
// Based on inputs decide :
// What control signals to issue,
// and what next state to take
endmodule

 Outline of a Controller

Verilog Digital System Design

Z. Navabi, 2006 11
 Sequential Multiplier
Multiplication An add-and-shift
begins with the Sequential When both bytes
start pulse. Multiplier are outputed.

done
start
Multiplier lsb-out
Clk
msb-out

For the most-significant

datapath byte
An 8-bit bidirectional I/O
for inputing it’s 8-bit operands
 Multiplier Block Diagram
and outputing its 16-bit output
one byte at a time.
Verilog Digital System Design
Z. Navabi, 2006 12
 Sequential Multiplier

Sequential
Multiplier

Shift-and-add Sequential
Multiplier
Multiplication Multiplier
Testing
Process Design

Verilog Digital System Design

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Shift-and-add Multiplication Process

Sequential
Multiplier

Shift-and-add
Shift-and-add Sequential
Multiplier
Multiplication Multiplier
Testing
Process
Process Design

Verilog Digital System Design

Z. Navabi, 2006 14
 Shift-and-add Multiplication Process
Depending on bit i of
operand A, either operand
B: 1 0 1 1 0 1 1 0
B is added to the collected A: 1 0 0 1 0 1 0 0
partial result and then
00000000
shifted to the right
(when bit i is 1)
00000000
Or (when bit i is 0) the
10110110
collected partial result
00000000 is shifted one place to
10110110 the right without being
00000000 added to B.
00000000
10110110
110100100111000
 Manual Binary Multiplication
Verilog Digital System Design
Z. Navabi, 2006 15
Shift-and-add Multiplication Process
t=0

P: 0 0 0 0 A: 1 0 0 1
A and B

B: 1 1 0 1

t=1 0000+1101 01101 t=2 0110+0000 00110

0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0

1 1 0 1 1 1 0 1

t=3 0011+0000 00011 t=4 0001+1101 01110

0 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1

1 1 0 1 1 1 0 1 Result

 Hardware Oriented Multiplication Process

Verilog Digital System Design
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Shift-and-add Multiplication Process

t=0

P: 0 0 0 0 A: 1 0 0 1
A and B
Because A[0] is 1, the partial
B: 1 1 0 1
sum of B + P is calculated.

 Hardware Oriented Multiplication Process (Continued)

Verilog Digital System Design

Z. Navabi, 2006 17
Shift-and-add Multiplication Process
t=1 0000+1101 01101

0 1 1 0 1 1 0 0

1 1 0 1 Because A[0] is 0,
0000 + P is calculated
t=2 0110+0000 00110

0 0 1 1 0 1 1 0

The right most bit of

1 1 0 1 which is shifted into A,
and the rest replace P
 Hardware Oriented Multiplication Process (Continued)
Verilog Digital System Design
Z. Navabi, 2006 18
Shift-and-add Multiplication Process
t=3 0011+0000 00011

0 0 0 1 1 0 1 1

1 1 0 1

t=4 0001+1101 01110

0 1 1 1 0 1 0 1

The least significant 4 bits of

1 1 0 1 Result the multiplication result
become available in A and the
 Hardware Oriented Multiplication Process (Continued)
most-significant bits in P.
Verilog Digital System Design
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 Sequential Multiplier Design

Sequential
Multiplier

Shift-and-add Sequential
Sequential Multiplier
Multiplication Multiplier
Testing
Process Design
Design

Verilog Digital System Design

Z. Navabi, 2006 20
Sequential Multiplier Design
Sequential
Multiplier Design

Control Data Multiplier

Partitioning Datapath

Datapath Multiplier
Description Controller

Top-Level Code
of the Multiplier
Verilog Digital System Design
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Control Data Partitioning
Sequential
Multiplier Design

Control Data Multiplier

Partitioning Datapath

Datapath Multiplier
Description Controller

Top-Level Code
of the Multiplier
Verilog Digital System Design
Z. Navabi, 2006 22
 Control Data Partitioning
Data part consists of
registers, logic units, and
their interconnecting buses.
lsb_out
msb_out
Datapath
databus clr_P
done
load_P
8 load_B
msb_out
lsb_out
sel_sum
load_A
shift_A

A0

start

 Datapath and Controller On the rising edge of the

system clock, the controller
goes into a new state.
Verilog Digital System Design
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 Multiplier Datapath
Sequential
Multiplier Design

Control Data Multiplier

Multiplier
Partitioning Datapath

Datapath Multiplier
Description Controller

Top-Level Code
of the Multiplier
Verilog Digital System Design
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 Selects carry-out from

Multiplier Datapath the adder or 0 depending

on the value of sel_sum
Adder co
sel_sum

Multiplexer
data
B sum
load_B

clk

clr_P

ShiftAdd
P A

load_P

8-bit Registers
A0
load_A
shift_A
msb_out 8-bit Shift Register
ShiftAdd[0]
lsb_out

Tri-state Buffers
 Multiplier Block Diagram
Verilog Digital System Design
Z. Navabi, 2006 25
Datapath Description
Sequential
Multiplier Design

Control Data Multiplier

Partitioning Datapath

Datapath Multiplier
Description Controller

Top-Level Code
of the Multiplier
Verilog Digital System Design
Z. Navabi, 2006 26
 Datapath Description
module datapath ( input clk, clr_P, load_P,
load_B, msb_out, lsb_out,
sel_sum, load_A, shift_A,
inout [7:0] data, output A0 );

wire [7:0] sum, ShiftAdd;

reg [7:0] A, B, P;
wire co;

...............................
...............................

 Datapath Verilog Code

Verilog Digital System Design
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 Datapath DescriptionRepresents
register B

always @( posedge clk ) if (load_B) B <= data;

always @( posedge clk )
if (load_P) P <= {co&sel_sum, ShiftAdd[7:1]};

assign { co, sum } = P + B; Represents register P

Represents
the 8-bit for the partial result
adder

always @( posedge clk )

case ( { load_A, shift_A } ) Implements the
8-bit shift-register
2'b01 : A <= { ShiftAdd[0], A[7:1] }; for operand A
2'b10 : A <= data;
Shifts A contents
default : A <= A;
endcase Loads A with data

 Datapath Verilog Code (Continued)

Verilog Digital System Design
Z. Navabi, 2006 28
 Datapath Description

...............................
Multiplexer for
assign A0 = A[0];
selection of sum or P

assign ShiftAdd = clr_P ? 8'h0 :

( ~sel_sum ? P : sum );

assign data = lsb_out ? A : 8'hzz;

assign data = msb_out ? P : 8'hzz;

endmodule 2 sets of tri-state buffers

driving the bidirectional
 Datapath Verilog Code (Continued) data bus of the datapath
Verilog Digital System Design
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Multiplier Controller
Sequential
Multiplier Design

Control Data Multiplier

Partitioning Datapath

Datapath Multiplier
Description Controller

Top-Level Code
of the Multiplier
Verilog Digital System Design
Z. Navabi, 2006 30
 Datapath Description
The multiplier
The multiplier waits forcontroller
`define idle 4'b0000 is a loading
start while finite state
A machine
`define init 4'b0001 that has 2 starting states,
Multiplier loads B
`define m1 4'b0010 8 multiplication states,
`define m2 4'b0011 and 2 ending states.
`define m3 4'b0100 The multiplier performs
`define m4 4'b0101 add-and-shift of P+B, or
`define m5 4'b0110 P+0, depending on A0
`define m6 4'b0111
States and
`define m7 4'b1000
their binary assignments
`define m8 4'b1001
The 2 halves of the result
`define rslt1 4'b1010
are put on databus.
`define rslt2 4'b1011

 Multiplier Control States

Verilog Digital System Design
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 Declares signals that

Multiplier Controller connect to datapath ports

module controller ( input clk, start, A0,

output reg clr_P, load_P, load_B, msb_out,
lsb_out, sel_sum,
output reg load_A, Shift_A, done);
reg [3:0] current; always block to issue
control signals and make
always @ ( negedge clk ) begin state transitions
clr_P = 0; load_P = 0; load_B = 0; msb_out = 0;
lsb_out = 0;
sel_sum = 0; load_A = 0; Shift_A = 0; done = 0;
..................................
Eliminating unwanted
All control signal outputs latches that may be
are Verilog
set to their
Codeinactive values.
of Controller generated by a synthesis
Verilog Digital tool for
System these outputs.
Design
Z. Navabi, 2006 32
 Multiplier Controller
The currently active state
case ( current ) of the machine
`idle :
if (~start) begin
current <= `idle;
done = 1;
end else begin To clear the P register
current <= `init;
To Load A load_A = 1; clr_P = 1; load_P = 1;
end
`init : begin
current <= `m1;
load_B = 1; end

 Verilog Code of Controller (Continued)

Verilog Digital System Design
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 Multiplier Controller

...............................
`m1, `m2, `m3, `m4, `m5, `m6, `m6, `m7, `m8:
begin
current <= current + 1;
Shifting A Shift_A = 1; load_P = 1; Loading P

if (A0) sel_sum = 1;
Asserting sel_sum
end
...............................

 Verilog Code of Controller (Continued)

Verilog Digital System Design

Z. Navabi, 2006 34
 Multiplier Controller
`rslt1 : begin In the result states,
current <= `rslt2; lsb_out and
lsb_out = 1; msb_out
are asserted in two
end
consecutive clocks
`rslt2 : begin in
current <= `idle; order to put A and P
msb_out = 1; on the data bus
end respectively.
default : current <= `idle;
endcase
end
endmodule

 Verilog Code of Controller (Continued)

Verilog Digital System Design
Z. Navabi, 2006 35
Top-Level Code of the Multiplier
Sequential
Multiplier Design

Control Data Multiplier

Partitioning Datapath

Datapath Multiplier
Description Controller

Top-Level
Top-Level Code
of the Multiplier
of the Multiplier
Verilog Digital System Design
Z. Navabi, 2006 36
Top-Level Code of the Multiplier
module Multiplier ( input clk, start,
inout [7:0] databus,
output lsb_out, msb_out, done );
wire clr_P, load_P, load_B, msb_out, lsb_out,
sel_sum, load_A, Shift_A;

datapath dpu( clk, clr_P, load_P, load_B,

msb_out, lsb_out, sel_sum, load_A,
Shift_A, databus, A0 );
controller cu( clk, start, A0, clr_P, load_P,
load_B, msb_out, lsb_out,
sel_sum, load_A, Shift_A, done
);
endmodule Datapath and controller
 Top-Level Multiplier Code
modules are instantiated.
Verilog Digital System Design
Z. Navabi, 2006 37
 Multiplier Testing

Sequential
Multiplier

Shift-and-add Sequential
Multiplier
Multiplication Multiplier
Testing
Testing
Process Design

Verilog Digital System Design

Z. Navabi, 2006 38
 Multiplier Testing
timescale 1ns/100ps
An auto-check
interactive testbench for
module test_multiplier; the sequential multiplier
reg clk, start, error; A bidirectional bus,
declared as wire for reading
wire [7:0] databus;
wire lsb_out, msb_out, done;
reg [7:0] mem1[0:2], mem2[0:2];
reg [7:0] im_data, opnd1, opnd2;
reg [15:0] expected_result, multiplier_result;
integer indx;
Declared for writing to the
What is calculated
............................... The result read
bidirectional databus Inputs and outputs
in the testbench
............................... from the multiplier
of the multiplier

 Multiplier Testbench Outline

Verilog Digital System Design
Z. Navabi, 2006 39
 Multiplier Testing
Read data files data1.dat
...............................
and data2.dat and apply
Multiplier uut ( clk, start, databus, lsb_out,
data
Apply to databus
start to start
msb_out, done ); the
multiplication
Calculate
initial begin: Apply_data Wait//Figure
... end for multiplication
8.11to
expected result
complete, and collect the
initial begin: Apply_Start ... end //Figure
calculated 8.12
result
Compare expected and
initial begin: Expected_Result... end //Figure8.13
calculated results and issue
always @(posedge clk) begin: Actual_Result
error if they do ... end
not match
// Figure 8.14
always @(posedge clk) begin: Compare_Results...end
// Figure 8.15
Above tasksthree
Applies are timed
rounds of test
always #50 clk = ~clk;
independently,
to theatMultiplier
the same module.
time,
assign databus=im_data;
an always block
In each generates
round, data isa applied
endmodule
periodic signal
to the on clk
module that test and
under
 Multiplier Testbench Outline clocks theare
results multiplier.
read and compared
Verilog Digital System Design with the expected results.
Z. Navabi, 2006 40
 Multiplier Testing
Multiplier
Testing

Reading Applying
Data Files Start

Calculating Reading
Expected Result Multiplier Output

Comparing
Results
Verilog Digital System Design
Z. Navabi, 2006 41