• Control when R Gated R-S latch

and S inputs
matter
– otherwise, the R' R
Q
slightest glitch
enable'
on R or S while Q'
enable is low S' S
could cause
change in value
Set Reset
stored 100

S'
R'
Enable active low!!
enable'
Q
Q'
 Master-slave structure
• Break flow by alternating clocks (like an air-lock)
– use positive clock to latch inputs into one R-S latch
– use negative clock (‘0’) to change outputs with another
R-S latch
• View pair as one basic unit
– master-slave flip-flop
– twice as much logic
– output changes a few gate delays after the falling edge
of clock
master stage slave stage
P’
R R Q’ R Q’

S S Q S Q
P
CLK
 The 1s catching problem
• In first R-S stage of master-slave FF
– 0-1-0 glitch on R or S while clock is high is
"caught" by master stage
– leads to constraints on logic to be hazard-free (no
master stage slave stage
glitch at output) P’
R R Q’ R Q’
S S Q S Q
1s P
Set Reset catch CLK

S
R
CLK
P Master
P’ Outputs
Q Slave
Q’ Outputs
 D flip-flop-negative edge trigged
• Make S and R complements of each other
– eliminates 1s catching problem
– can't just hold previous value
(must have new value ready every clock period)
– value of D just before clock goes low is what is
stored in flip-flop – Negative edge trigged!!!
master stage slave stage
P’
R Q’ R Q’ Q’

D S Q S Q Q
P
CLK
Functionality table for the D-flip-flop based
on the master-slave princip

Clock-CLK Input Output - Q

D D

1 X Last Q

0 X Last Q
 D latch

Function table

C is as an enable active high

D Q

QN
C
D-latch based on Nand gates – same functionality as above!
D-Latch timing diagram

Signals applied

Q
Last Q

Initial state either 0 or 1, we don’t know

 Clock signals
• Very important with most sequential circuits
– State variables change state at clock edge.
Rising edge (Positive)-edge
triggered D flip-flop
Note in the BOOK
They use negative edge
Trigged Flip flops!!

QMN

Logic Symbol
D-flip-flop
Q changes on edge to
value on D present
before edge!!!!!
D-Flip Flop positive edge trigged

Function table
 Edge-triggered flip-flops (cont’d)
• Positive edge-triggered
– inputs sampled on rising edge; outputs change
after rising edge – used in the CPLD device!
• Negative edge-triggered flip-flops (master
slave based)
– inputs sampled on falling100
edge; outputs change
D
after falling edge
CLK
Qpos
positive edge-triggered FF
Qpos’
Qneg
negative edge-triggered FF
Qneg’
 Comparison of latches and flip-
flops
D Q

CLK D

positive
edge-triggered
flip-flop CLK

Qedge

D Q
G Qlatch
CLK
transparent
(level-sensitive)
latch behavior is the same unless input changes
while the clock is high
 D-flip flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFFDemo is
Port( D : in std_logic;
Clk : in std_logic;
Q : out std_logic);
end DFFDemo;

architecture Behavioral of DFFDemo is

begin
process(Clk)
begin
if rising_edge(Clk) then --when rising
edge update output
Q <= D;
end if;
end process;
end Behavioral;
D flip-flop with enable and Clear
D Flip-Flop with enable and synchronous clear

D
Q

EN

CLR

CLK

Function table
CLR EN D CLK Q
0 1 0 0
0 1 1 1
X X X 1 Last Q
X X X 0 Last Q
X 0 X Last Q
1 0 X 0 Last Q
1 1 1 1
1 1 X 1 0
library IEEE; D flip flop with enable and reset in VHDL
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFFERSDemo is
Port( D : in std_logic;
Clk : in std_logic;
En, Rst, Set : in std_logic;
Q : out std_logic);
end DFFERSDemo;
architecture Behavioral of DFFERSDemo
is
begin
process(En, Clk)
begin
if En = '1' then
if rising_edge(Clk) then
if clr = '1' then
Q <= '0';
else
Q <= D;
end if;
end if;
end if;
end process;
end Behavioral;
T flip-flop
 T-Flip flop in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TFFDemo is
Port( Clk : in std_logic;
Q : out std_logic);
end TFFDemo;

architecture Behavioral of TFFDemo is

signal Temp : std_logic := '0'; --temporary
variable initialised to 0
begin
process(en,Clk)
begin
If en=‘1’ then
if rising_edge(Clk) then --when rising edge
Temp <= not Temp; --the temp variable
is inverted
end if;
End if;
end process;
Q <= Temp; --concurrently the output is
updated
end Behavioral;
 Registers
• Collections of flip-flops with similar controls and
logic
– stored values somehow related (for example, form
binary value)
– share clock, reset, and set lines
– similar logic at each stage
• Examples
– registers
OUT1 OUT2 OUT3 OUT4
– counters
"0"

R S R S R S R S
D- flip-flops with D Q D Q D Q D Q
R: reset CLK
S: set
IN1 IN2 IN3 IN4
Not active for R=0 &S=0
 Counters
• Sequences through a fixed set of patterns
– in this case, 1000, 0100, 0010, 0001
– if one of the patterns is its initial state (by
loading or set/reset)

OUT1 OUT2 OUT3 OUT4

IN D Q D Q D Q D Q
CLK
 Activity
• How does this counter work?

OUT1 OUT2 OUT3 OUT4

IN D Q D Q D Q D Q
CLK

 Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
 Known as Mobius (or Johnson) counter
 Binary counter
• Logic between registers – synchronizing to
clk!!!
• XOR decides when bit should be toggled
– always for low-order bit,
only when first bit is true for second bit,
and so on
OUT1 OUT2 OUT3 OUT4

D Q D Q D Q D Q
CLK

"1"
 Four-bit binary synchronous up-
counter
• Standard component with many applications
– positive edge-triggered FFs w/ synchronous load and clear inputs
– parallel load data from D, C, B, A
– enable inputs: must be asserted to enable counting
– RCO: ripple-carry out used for cascading counters
• high when counter is in its highest state 1111 EN

• implemented using an AND gate D

C RCO
B
A QD
(2) RCO goes high QC
LOAD QB
CLK QA
CLR
(3) High order 4-bits
are incremented

(1) Low order 4-bits = 1111

outputs
 Offset counters
• Starting offset counters – use of synchronous load "1" EN
RCO
– e.g., 0110, 0111, 1000, 1001, "0"
"1"
D
C
QD
QC
1010, 1011, 1100, 1101, 1111, 0110, . . . "1"
"0"
B
A
QB
QA
LOAD
CLK
"0" CLR

• Ending offset counter – comparator for ending value

"1" EN
RCO
– e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000 "0" D QD
"0" C QC
"0" B QB
"0" A QA
LOAD
CLK
CLR

• Combinations of the above (start and stop value)

 Binary counters in VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count_8bit is
Port ( en,clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0));
end count_8bit;
architecture Behavioral of count_8bit is
signal Count : std_logic_vector(7 downto 0)=”0000”; Count is a local varibale
begin
process(En, Clk)
– initialized due to
begin simulation
if En = '1' then
if rising_edge(Clk) then
Count <= Count + 1; -- Count is incremented at clk when en
end if;
end if;
end process;
Q <= Count; Output Q is updated in concurently with the count process
end Behavioral;
 Testing sequential logic
• Have a look in the example for the 8 bit
counter placed into the Campusnet
 Sequential logic summary
• Fundamental building block of circuits with state
– latch and flip-flop
– R-S latch, R-S master/slave, D master/slave, edge-
triggered D flip-flop
• Timing methodologies
– use of clocks
• Basic registers
– registers
– counters
• Hardware description languages and sequential
logic
 Exercise
enable Q(3:0)
clk
rco

•Write a VHDL module for a 4 bit binary

counter
•Requirements:
–Rco has to go high when count is 12 and then
the counter should start counting again from 0
–Enable enable counting when high else the
counter stops
•Write a test bench and check the
behaviour Engineering College of Copenhagen -
osc 2006-10-05